LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 51

• Manufacturer Part Number: LAN9211-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9211-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current (max): 86 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 86mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1049-6

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9211
30:26
25:24
23:21
20:16
15:14
BITS
10:0
31
13
12
11
TX COMMAND ‘A’
Interrupt on Completion. When set, the TXDONE flag will be asserted when the current buffer has
been fully loaded into the TX FIFO. This flag may be optionally mapped to a host interrupt.
Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility.
Buffer End Alignment. This field specifies the alignment that must be maintained on the last data
transfer of a buffer. The host will add extra DWORDs of data up to the alignment specified in the
table below. The LAN9211 will remove the extra DWORDs. This mechanism can be used to maintain
cache line alignment on host processors.
Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility
Data Start Offset (bytes). This field specifies the offset of the first byte of TX data. The offset value
can be anywhere from 0 bytes to 31 a Byte offset.
Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility
First Segment (FS). When set, this bit indicates that the associated buffer is the first segment of the
packet.
Last Segment. When set, this bit indicates that the associated buffer is the last segment of the
packet
Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility.
Buffer Size (bytes). This field indicates the number of bytes contained in the buffer following this
command. This value, along with the Buffer End Alignment field, is read and checked by the LAN9211
and used to determine how many extra DWORD’s were added to the end of the Buffer. A running
count is also maintained in the LAN9211 of the cumulative buffer sizes for a given packet. This
cumulative value is compared against the Packet Length field in the TX command ‘B’ word and if
they do not correlate, the TXE flag is set.
Note:
The buffer size specified does not include the buffer end alignment padding or data start
offset added to a buffer.
[25]
0
0
1
1
Table 3.12 TX Command 'A' Format
[24]
0
1
0
1
DATASHEET
DESCRIPTION
51
16-byte alignment
32-byte alignment
4-byte alignment
End Alignment
Reserved
Revision 2.7 (03-15-10)