LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 17

IC ETHERNET CTLR SGL CHIP 56-QFN

LAN9211-ABZJ

Manufacturer Part Number
LAN9211-ABZJ
Description
IC ETHERNET CTLR SGL CHIP 56-QFN
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet

Specifications of LAN9211-ABZJ

Controller Type
Ethernet Controller
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-QFN
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
IEEE 802.3 or IEEE 802.3u
Data Rate
10 Mbps or 100 Mbps
Supply Voltage (max)
5 V
Supply Voltage (min)
3.3 V
Supply Current (max)
86 mA
Maximum Operating Temperature
+ 70 C
Ethernet Connection Type
100BASE-TX or 10BASE-T
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
No. Of Ports
2
Ethernet Type
IEEE 802.3 / 802.3u
Interface Type
HBI
Supply Current
86mA
Supply Voltage Range
2.97V To 3.63V
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1049-6

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Part Number
Manufacturer
Quantity
Price
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Manufacturer:
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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9211
Auto-MDIX Enable
Crystal 1, Clock In
Wakeup Indicator
No Connect
Crystal 2
NAME
Reset
XTAL1/CLKIN
AMDIX_EN
SYMBOL
nRESET
XTAL2
PME
NC
Table 2.4 System and Power Signals
BUFFER
O8/OD8
OCLK
TYPE
lCLK
(PU)
(PU)
IS
I
DATASHEET
17
PINS
NUM
1
1
1
1
1
1
External 25MHz Crystal Input. This pin can also
No Connect. This pin must be left open.
be connected to single-ended TTL oscillator
(CLKIN). If this method is implemented, XTAL2
should be left unconnected.
External 25MHz Crystal output.
Active-low reset input. Resets all logic and
registers within the LAN9211. This signal is
pulled high with a weak internal pull-up resistor.
Note:
When programmed to do so, is asserted when
the LAN9211 detects a wake event and is
requesting the system to wake up from the
associated sleep state. The polarity and buffer
type of this signal is programmable.
Note:
Enables Auto-MDIX. Pull high or leave
unconnected to enable Auto-MDIX, pull low to
disable Auto-MDIX.
The LAN9211 must be reset on power-
up via nRESET or following power-up
via a soft reset (SRST). The LAN9211
must always be read at least once
after reset, or upon return from a
power-saving state or write operations
will not function. See
"Detailed Reset Description," on
page 46
Detection of a Power Management
Event, and assertion of the PME
signal will not wakeup the LAN9211.
The LAN9211will only wake up when it
detects a host write cycle (assertion of
nCS and nWR). Although any write to
the LAN9211, regardless of the data
written, will wake-up the device when
it is in a power-saving mode, it is
required that the BYTE_TEST register
be used for this purpose.
DESCRIPTION
for additional information
Section 3.11,
Revision 2.7 (03-15-10)

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