LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 54

• Manufacturer Part Number: LAN9211-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9211-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current (max): 86 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 86mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1049-6

Revision 2.7 (03-15-10)
3.12.5
BITS
6:3
10
9
8
7
2
1
0
No Carrier. When set, this bit indicates that the carrier signal from the transceiver was not present
during transmission.
Note:
Late Collision. When set, indicates that the packet transmission was aborted after the collision
window of 64 bytes.
Excessive Collisions. When set, this bit indicates that the transmission was aborted after 16
collisions while attempting to transmit the current packet.
Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility.
Collision Count. This counter indicates the number of collisions that occurred before the packet was
transmitted. It is not valid when excessive collisions (bit 8) is also set.
Excessive Deferral. If the deferred bit is set in the control register, the setting of the excessive
deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times
during transmission.
Reserved. This bit is reserved. Always write zero to this bit to guarantee future compatibility.
Deferred. When set, this bit indicates that the current packet transmission was deferred.
Calculating Actual TX Data FIFO Usage
The following rules are used to calculate the actual TX data FIFO space consumed by a TX Packet:
TX command 'A' is stored in the TX data FIFO for every TX buffer
TX command 'B' is written into the TX data FIFO when the First Segment (FS) bit is set in TX
command 'A'
When TX checksum is enabled, the 4-byte TX checksum preamble is written into TX Data FIFO.
Any DWORD-long data added as part of the “Data Start Offset” is removed from each buffer before
the data is written to the TX data FIFO. Any data that is less than 1 DWORD is passed to the TX
data FIFO.
Payload from each buffer within a Packet is written into the TX data FIFO.
Any DWORD-long data added as part of the End Padding is removed from each buffer before the
data is written to the TX data FIFO. Any end padding that is less than 1 DWORD is passed to the
TX data FIFO
During 10/100 Mbps full-duplex transmission, the value of this bit is invalid and should be
ignored.
DATASHEET
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
DESCRIPTION
54
SMSC LAN9211
Datasheet