LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 44

• Manufacturer Part Number: LAN9211-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9211-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current (max): 86 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 86mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1049-6

Revision 2.7 (03-15-10)
MAC and Host
Internal Clock
Management
MAC Power
Interface
BLOCK
Device
PHY
Note 3.16 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the
A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the
LAN9211 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host
is required to check the READY bit and verify that it is set before attempting any other reads or writes
of the device. Before the LAN9211 is fully awake from this state the EDPWRDOWN bit in register 17
of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit
until the READY bit is set. After clearing the EDPWRDOWN bit the LAN9211 is ready to resume normal
operation. At this time the WUPS field can be cleared.
setting of PME_EN.
(NORMAL OPERATION)
Full ON
Full ON
Full ON
Full ON
Table 3.10 Power Management States
D0
KEY
CLOCK ON
BLOCK DISABLED – CLOCK ON
FULL OFF
DATASHEET
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
RX Power Mgmt. Block
44
Full ON
Full ON
(WOL)
OFF
D1
On
Energy Detect Power-Down
(ENERGY DETECT)
OFF
OFF
OFF
D2
SMSC LAN9211
Datasheet