LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 95

• Manufacturer Part Number: LAN9211-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9211-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current (max): 86 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 86mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1049-6

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9211
5.3.15
31-30
28-16
BITS
BITS
15-0
[22]
4:3
2:0
29
0
0
0
0
1
1
1
1
Reserved
GP Timer Enable (TIMER_EN). When a one is written to this bit the GP
Timer is put into the run state. When cleared, the GP Timer is halted. On
the 1 to 0 transition of this bit the GPT_LOAD field will be preset to FFFFh.
Reserved
General Purpose Timer Pre-Load (GPT_LOAD). This value is pre-loaded
into the GP-Timer.
GPO Data 3-4 (GPODn). The value written is reflected on GPOn.
GPIO Data 0-2 (GPIODn). When enabled as an output, the value written is
reflected on GPIOn. When read, GPIOn reflects the current state of the
corresponding GPIO pin.
GPO3 – bit 3
GPO4 – bit 4
GPIO0 – bit 0
GPIO1 – bit 1
GPIO2 – bit 2
GPT_CFG-General Purpose Timer Configuration Register
This register configures the General Purpose timer. The GP Timer can be configured to generate host
interrupts at intervals defined in this register.
[21]
0
0
1
1
0
0
1
1
Offset:
[20]
0
1
0
1
0
1
0
1
Table 5.4 EEPROM Enable Bit Definitions
DESCRIPTION
DESCRIPTION
8Ch
EEDIO FUNCTION
DATASHEET
TX_CLK
TX_EN
TX_EN
EEDIO
GPO3
GPO3
95
Size:
Reserved
Reserved
32 bits
EECLK FUNCTION
TYPE
RX_CLK
R/W
R/W
EECLK
RX_DV
RX_DV
RO
RO
GPO4
GPO4
TYPE
R/W
R/W
Revision 2.7 (03-15-10)
DEFAULT
DEFAULT
FFFFh
000
0
-
-
00