FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 10

IC CTRLR SUPER I/O FLPPY 100TQFP

FDC37C669-MT

Manufacturer Part Number
FDC37C669-MT
Description
IC CTRLR SUPER I/O FLPPY 100TQFP
Manufacturer
SMSC
Datasheet

Specifications of FDC37C669-MT

Controller Type
I/O Controller
Interface
ISA Host
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
25mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1008

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FDC37C669-MT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIN NO.
TQFP
80,90
85,87
84,86
QFP/
nData Set Ready
nData Carrier
Detect
nRing Indicator
NAME
nDSR1
nDSR2
nDCD1
nDCD2
nRI1
nRI2
DESCRIPTION OF PIN FUNCTIONS
SYMBOL
PARALLEL PORT INTERFACE
BUFFER
TYPE
I
I
I
10
Active low Data Set Ready inputs for the serial
port.
UART that the modem is ready to establish
the communication link.
monitor the status of nDSR signal by reading
bit 5 of Modem Status Register (MSR).
nDSR signal state change from low to high
after the last MSR read will set MSR bit 1 to a
1. If bit 3 of Interrupt Enable Register is set,
the interrupt is generated when nDSR
changes state. Note: Bit 5 of MSR is the
complement of nDSR.
Active low Data Carrier Detect inputs for the
serial port. Handshake signal which notifies
the UART that carrier signal is detected by the
modem. The CPU can monitor the status of
nDCD signal by reading bit 7 of Modem Status
Register (MSR). A nDCD signal state change
from low to high after the last MSR read will
set MSR bit 3 to a 1. If bit 3 of Interrupt
Enable Register is set, the interrupt is
generated when nDCD changes state. Note:
Bit 7 of MSR is the complement of nDCD.
Active low Ring Indicator inputs for the serial
port.
UART that the telephone ring signal is
detected by the modem.
monitor the status of nRI signal by reading bit
6 of Modem Status Register (MSR). A nRI
signal state change from low to high after the
last MSR read will set MSR bit 2 to a 1. If bit 3
of Interrupt Enable Register is set, the
interrupt is generated when nRI changes
state. Note: Bit 6 of MSR is the complement
of nRI.
Handshake signal which notifies the
Handshake signal which notifies the
DESCRIPTION
The CPU can
The CPU can
A

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