FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 126

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

CR08
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 08H.
The default value of this register after power up is 00H.
This is the lower 4 bits (ADRA7:4) for the ADRx address
decode.
default to 0000b.
CR0A
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 0AH. The
default
CR0B
This register can only be ac1cessed in the Configuration
Mode and after the CSR has been initialized
0BH.
DRT1
D7
D7
RESERVED - READ ONLY 0 HEX
FDD3
The non-programmable
Upper Address Decode requirements : nCS='0' is required to qualify the ADRx output.
DRT0
D6
D6
The
value
default
DRT1
D5
D5
FDD2
address
of
D7
0
0
1
1
value
DRT0
Table 54 - CR0A
D4
D4
bits
D6
0
1
0
1
Table 55 - CR0B
this
3:0
to
of
THR3
DRT1
126
D3
D3
ADRx Configuration
16 byte block decode
8 Byte block decode
ADRx disabled
A[3:0]=XXXXb
1 Byte decode
A[3:0]=0XXXb
A[3:0]=0000b
CR09
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 09H. The
default value of this register after power up is 00H. This
is the upper 3 bits (ADRA10:8) (D2 - MSB, D0 - LSB) for
the ADRx address decode. ADRx Config (bits 7:6) define
the configuration of the ADRx decoder as follows:
register after power up is 00H. This byte defines the
FIFO threshold for the ECP mode parallel port.
this register after power up is 00H. This register indicates
the data rate table used for each drive. Refer to CR1F for
Drive Type register.
ECP F I F O T H R E S H O L D
FDD1
THR2
DRT0
D2
D2
THR1
DRT1
D1
D1
FDD0
THR0
DRT0
D0
D0