FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 80

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

FIFO INTERRUPT MODE OPERATION
When the RCVR FIFO and receiver interrupts are
enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR
interrupts occur as follows:
A. The receive data available interrupt will be issued
B. The IIR receive data available indication also occurs
C. The receiver line status interrupt (IIR=06H), has
D. The data ready bit (LSR bit 0)is set as soon as a
When RCVR FIFO and receiver interrupts are enabled,
RCVR FIFO timeout interrupts occur as follows:
A. A FIFO timeout interrupt occurs if all the following
when the FIFO has reached its programmed trigger
level; it is cleared as soon as the FIFO drops below its
programmed trigger level.
when the FIFO trigger level is reached. It is cleared
when the FIFO drops below the trigger level.
higher priority than the received data available
(IIR=04H) interrupt.
character is transferred from the shift register to the
RCVR FIFO. It is reset when the FIFO is empty.
conditions exist:
- At least one character is in the FIFO
- The most recent serial character received was
- The most recent CPU read of the FIFO was longer
This will cause a maximum character received to
interrupt issued delay of 160 msec at 300 BAUD with
a 12 bit character.
longer than 4 continuous character times ago. (If 2
stop bits are programmed, the second one is
included in this time delay.)
than 4 continuous character times ago.
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B. Character times are calculated by using the RCLK
C. When a timeout interrupt has occurred it is cleared
D. When a timeout interrupt has not occurred the timeout
When the XMIT FIFO and transmitter interrupts are
enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts
occur as follows:
A. The transmitter holding register interrupt (02H) occurs
B. The transmitter FIFO empty indications will be
Character timeout and RCVR FIFO trigger level interrupts
have the sme priority as the current received data
available interrupt; XMIT FIFO empty has the same
priority as the current transmitter holding register empty
interrupt.
FIFO POLLED MODE OPERATION
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to
zero puts the UART in the FIFO Polled
operation. Since the RCVR and
input for a clock signal (this makes the delay
proportional to the baudrate).
and the timer reset when the CPU reads one
character from the RCVR FIFO.
timer is reset after a new character is received or after
the CPU reads the RCVR FIFO.
when the XMIT FIFO is empty; it is cleared as soon
as the transmitter holding register is written to (1 of 16
characters may be written to the XMIT FIFO while
servicing this interrupt) or the IIR is read.
delayed 1 character time minus the last stop bit time
whenever the following occurs: THRE=1 and there
have not been at least two bytes at the same time in
the transmitter FIFO since the last THRE=1. The
transmitter interrupt after changing FCR0 will be
immediate, if it is enabled.
Mode of