FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 6

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

PIN NO.
41-43,
21,52,
22,36,
TQFP
48-51
53-56
28-34
QFP/
44
45
46
97
99
96
35
Data Bus 0-7
nI/O Read
nI/O Write
Address Enable
I/O Address
DMA Request
A, B, C
nDMA
Acknowledge
A, B, C
Terminal Count
NAME
D0-D7
nIOR
nIOW
AEN
A0-A10
DRQ_A
DRQ_B
DRQ_C
nDACK_A
nDACK_B
nDACK_C
TC
DESCRIPTION OF PIN FUNCTIONS
SYMBOL
HOST PROCESSOR INTERFACE
BUFFER
TYPE
I/O24
O24
I
I
I
I
I
I
6
This active low signal is issued by the host
The data bus connection used by the host
microprocessor to transmit data to and from
the chip. These pins are in a high-impedance
state when not in the output mode.
This active low signal is issued by the host
microprocessor to indicate a read operation.
microprocessor to indicate a write operation.
Active high Address Enable indicates DMA
operations on the host data bus.
internally to qualify appropriate address
decodes.
These host address bits determine the I/O
address to be accessed during nIOR and
nIOW cycles. These bits are latched internally
by the leading edge of nIOR and nIOW. All
internal address decodes use the full A0 to
A10 address bits.
This active high output is the DMA request for
byte transfers of data between the host and
the chip. This signal is cleared on the last
byte of the data transfer by the nDACK signal
going low (or by nIOR going low if nDACK was
already low as in demand mode).
An active low input acknowledging the request
for a DMA transfer of data between the host
and the chip. This input enables the DMA
read or write internally.
This signal indicates to the chip that DMA data
transfer is complete.
when nDACK_x is low. In AT and PS/2 model
30 modes, TC is active high and in PS/2
mode, TC is active low.
DESCRIPTION
TC is only accepted
Used