FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 130

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

CR12-CR1D
These registers are reserved. The default value of these
registers after power up is 00H.
CR1E
This
Configuration Mode and after the CSR has been
Upper Address Decode requirements: nCS='0' and A10='0' are required to qualify the GAMECS output.
CR03, bit DB0 is the PWRGD/GAMECS control bit and overrides the selection made by the above configuration.
ADR9
DB7
register
ADR8
DB6
can
only be
ADR7
DB5
accessed
DB1
0
0
1
1
ADR6
DB4
DB0
in
0
1
0
1
the
ADR5
GAMECS Configuration
DB3
130
16 byte block decode,
8 Byte block decode,
GAMECS disabled
ADR[3:0] = XXXXb
ADR[3:0] = 0XXXb
ADR[3:0] = 0001b
1 Byte decode,
initialized to 1EH. The default value of this register after
power up is 80H. This register is used to select the base
address of the Game Chip Select decoder (GAMECS).
The GAMECS can be set to 48 locations, on 16 byte
boundaries from 100H-3F0H. To disable the GAMECS,
set DB1 and DB0 to zero.
ADR4
DB2
DB1
GAMECS Config
DB0