PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 111

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2455-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 24K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.5
Depending on the particular PIC18F2450/4450 device
selected, PORTE is implemented in two different ways.
For 40/44-pin devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5, RE1/AN6 and RE2/AN7) are
individually configurable as inputs or outputs. These
pins have Schmitt Trigger input buffers. When selected
as an analog input, these pins will read as ‘0’s.
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
The fourth pin of PORTE (MCLR/V
only pin. Its operation is controlled by the MCLRE Config-
uration bit. When selected as a port pin (MCLRE = 0), it
REGISTER 9-1:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3-0
Note 1:
Note:
U-0
—
2:
3:
PORTE, TRISE and LATE
Registers
implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,
read as ‘0’.
RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
Unimplemented in 28-pin devices; read as ‘0’.
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
Unimplemented: Read as ‘0’
RE3:RE0: PORTE Data Input bits
U-0
—
PORTE REGISTER
W = Writable bit
‘1’ = Bit is set
PP
U-0
—
/RE3) is an input
Advance Information
U-0
(1,2,3)
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RE3
R/W-x
functions as a digital input only pin; as such, it does not
have TRIS or LAT bits associated with its operation.
Otherwise, it functions as the device’s Master Clear input.
In either configuration, RE3 also functions as the
programming voltage input during programming.
EXAMPLE 9-5:
9.5.1
For 28-pin devices, PORTE is only available when
Master Clear functionality is disabled (MCLRE = 0). In
these cases, PORTE is a single bit, input only port
comprised of RE3 only. The pin operates as previously
described.
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
Note:
(1,2)
PIC18F2450/4450
PORTE
LATE
0Ah
ADCON1 ; for digital inputs
03h
TRISC
On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
PORTE IN 28-PIN DEVICES
RE2
R/W-0
(3)
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; Value used to
; initialize data
; direction
; Set RE<0> as inputs
; RE<1> as inputs
; RE<2> as outputs
INITIALIZING PORTE
x = Bit is unknown
RE1
R/W-0
(3)
DS39760A-page 109
RE0
R/W-0
(3)
bit 0