PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 92

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PIC18F2455-I/SP

Manufacturer Part Number
PIC18F2455-I/SP
Description
Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F2455-I/SP

A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
23
Interface
I2C/SPI/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
24K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2455-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F2450/4450
8.3
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request (Flag) registers (PIR1 and PIR2).
REGISTER 8-4:
DS39760A-page 90
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
PIR Registers
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty
TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full
Unimplemented: Read as ‘0’
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
R/W-0
ADIF
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
W = Writable bit
‘1’ = Bit is set
RCIF
R-0
Advance Information
TXIF
R-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
Note 1: Interrupt flag bits are set when an interrupt
2: User
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
CCP1IF
R/W-0
software
© 2006 Microchip Technology Inc.
x = Bit is unknown
TMR2IF
R/W-0
should
ensure
TMR1IF
R/W-0
bit 0
the

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