PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 316

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2455-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 24K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2450/4450
U
Universal Serial Bus ........................................................... 59
USB
USB. See Universal Serial Bus.
DS39760A-page 314
Address Register (UADDR) ..................................... 136
Associated Registers ............................................... 149
Buffer Descriptor Table ............................................ 137
Buffer Descriptors .................................................... 137
Class Specifications and Drivers ............................. 151
Descriptors ............................................................... 151
Endpoint Control ...................................................... 135
Enumeration ............................................................. 151
External Transceiver ................................................ 131
Eye Pattern Test Enable .......................................... 133
Firmware and Drivers ............................................... 148
Frame Number Registers ......................................... 136
Frames ..................................................................... 150
Internal Transceiver ................................................. 131
Internal Voltage Regulator ....................................... 133
Interrupts .................................................................. 143
Layered Framework ................................................. 150
Oscillator Requirements ........................................... 148
Output Enable Monitor ............................................. 133
Overview .......................................................... 129, 150
Ping-Pong Buffer Configuration ............................... 133
Power ....................................................................... 150
Power Modes ........................................................... 148
Pull-up Resistors ...................................................... 133
RAM ......................................................................... 136
Speed ....................................................................... 151
Status and Control ................................................... 130
Transfer Types ......................................................... 150
UFRMH:UFRML Registers ...................................... 136
Internal Voltage Regulator Specifications ................ 279
Module Specifications .............................................. 279
Address Validation ........................................... 140
Assignment in Different
BDnSTAT Register (CPU Mode) ..................... 138
BDnSTAT Register (SIE Mode) ....................... 140
Byte Count ....................................................... 140
Example ........................................................... 137
Memory Map .................................................... 141
Ownership ........................................................ 137
Ping-Pong Buffering ......................................... 141
Register Summary ........................................... 142
Status and Configuration ................................. 137
and USB Transactions ..................................... 143
Bus Power Only ............................................... 148
Dual Power with Self-Power
Self-Power Only ............................................... 148
Memory Map .................................................... 136
Buffering Modes ....................................... 142
Dominance ............................................... 148
Advance Information
W
Watchdog Timer (WDT) ........................................... 189, 201
WWW Address ................................................................ 315
WWW, On-Line Support ...................................................... 6
X
XORLW ............................................................................ 251
XORWF ........................................................................... 252
Associated Registers ............................................... 202
Control Register ....................................................... 201
During Oscillator Failure .......................................... 204
Programming Considerations .................................. 201
© 2006 Microchip Technology Inc.