PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 315

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2455-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 24K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Timer0 .............................................................................. 111
Timer1 .............................................................................. 115
Timer2 .............................................................................. 121
Timing Diagrams
© 2006 Microchip Technology Inc.
16-Bit Mode Timer Reads and Writes ...................... 112
Associated Registers ............................................... 113
Clock Source Edge Select (T0SE Bit) ...................... 112
Clock Source Select (T0CS Bit) ............................... 112
Operation ................................................................. 112
Overflow Interrupt .................................................... 113
Prescaler .................................................................. 113
Prescaler. See Prescaler, Timer0.
16-Bit Read/Write Mode ........................................... 117
Associated Registers ....................................... 119, 126
Interrupt .................................................................... 118
Operation ................................................................. 116
Oscillator .......................................................... 115, 117
Overflow Interrupt .................................................... 115
Resetting, Using a Special Event Trigger
TMR1H Register ...................................................... 115
TMR1L Register ....................................................... 115
Use as a Real-Time Clock ....................................... 118
Associated Registers ............................................... 122
Interrupt .................................................................... 122
Operation ................................................................. 121
Output ...................................................................... 122
PR2 Register ............................................................ 127
TMR2 to PR2 Match Interrupt .................................. 127
A/D Conversion ........................................................ 291
Asynchronous Reception ......................................... 165
Asynchronous Transmission .................................... 163
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 161
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 166
BRG Overflow Sequence ......................................... 161
Brown-out Reset (BOR) ........................................... 286
Capture/Compare/PWM (CCP) ................................ 288
CLKO and I/O .......................................................... 284
Clock/Instruction Cycle .............................................. 57
EUSART Synchronous Receive
EUSART Synchronous Transmission
External Clock (All Modes Except PLL) ................... 283
Fail-Safe Clock Monitor ............................................ 205
High/Low-Voltage Detect Characteristics ................ 280
High-Voltage Detect (VDIRMAG = 1) ...................... 186
Low-Voltage Detect (VDIRMAG = 0) ....................... 185
PWM Output ............................................................ 127
Reset, Watchdog Timer (WDT), Oscillator
Switching Assignment ...................................... 113
Layout Considerations ..................................... 118
Low-Power Option ........................................... 117
Using Timer1 as a Clock Source ..................... 117
Output (CCP) ................................................... 118
(Back to Back) ................................................. 163
Normal Operation ............................................ 166
(Master/Slave) ................................................. 289
(Master/Slave) ................................................. 289
Start-up Timer (OST) and Power-up
Timer (PWRT) .................................................. 285
Advance Information
Timing Diagrams and Specifications ............................... 283
Top-of-Stack Access .......................................................... 54
TQFP Packages and Special Features ........................... 209
TSTFSZ ........................................................................... 251
Two-Speed Start-up ................................................. 189, 203
Two-Word Instructions
TXSTA Register
Send Break Character Sequence ............................ 167
Slow Rise Time (MCLR Tied to V
Synchronous Reception
Synchronous Transmission ..................................... 168
Synchronous Transmission (Through TXEN) .......... 169
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 287
Transition for Entry to Idle Mode ............................... 38
Transition for Entry to SEC_RUN Mode .................... 34
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
Transition for Wake from Idle to
Transition for Wake from Sleep (HSPLL) .................. 37
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 36
USB Signal .............................................................. 290
Capture/Compare/PWM
CLKO and I/O Requirements ................................... 285
EUSART Synchronous Receive
EUSART Synchronous Transmission
External Clock Requirements .................................. 283
PLL Clock ................................................................ 284
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
USB Full-Speed Requirements ............................... 290
USB Low-Speed Requirements ............................... 290
Example Cases ......................................................... 58
BRGH Bit ................................................................. 157
V
(Master Mode, SREN) ..................................... 170
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 203
Run Mode .......................................................... 38
PRI_RUN Mode ................................................. 36
PRI_RUN Mode (HSPLL) .................................. 35
Requirements (CCP) ....................................... 288
Requirements .................................................. 289
Requirements .................................................. 289
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 286
Requirements .................................................. 287
PIC18F2450/4450
DD
Rise > T
PWRT
DD
DD
) ............................................ 47
) .......................................... 47
, V
DD
DD
DD
), Case 1 ...................... 46
), Case 2 ...................... 46
Rise T
DD
DS39760A-page 313
,
PWRT
) .............. 46