PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 127

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2455-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 24K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.3
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (CCP1M3:CCP1M0). At the same time, the
interrupt flag bit, CCP1IF, is set.
13.3.1
The user must configure the CCP1 pin as an output by
clearing the appropriate TRIS bit.
13.3.2
Timer1
Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
FIGURE 13-2:
© 2006 Microchip Technology Inc.
I/O latch)
Note:
Compare Mode
must
CCP1 PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC2 compare output latch to the
default low level.
TIMER1 MODE SELECTION
be
CCPR1H
TMR1H
running in
Comparator
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR1L
TMR1L
Timer
Compare
Match
mode,
Set CCP1IF
Advance Information
or
Special Event Trigger
CCP1CON<3:0>
(Timer1 Reset)
13.3.3
When the Generate Software Interrupt mode is chosen
(CCP1M3:CCP1M0 = 1010), the CCP1 pin is not
affected. Only a CCP interrupt is generated, if enabled,
and the CCP1IE bit is set.
13.3.4
The CCP module is equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the
(CCP1M3:CCP1M0 = 1011).
For the CCP module, the Special Event Trigger resets
the Timer1 register pair. This allows the CCPR1
registers to serve as a programmable period register
for the Timer1.
The Special Event Trigger for CCP1 can also start an
A/D conversion. In order to do this, the A/D converter
must already be enabled.
Output
Logic
4
Compare
PIC18F2450/4450
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
S
R
Q
Special
Output Enable
TRIS
Event
CCP1 pin
DS39760A-page 125
Trigger
mode