PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 145

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2455-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 24K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

14.5
The USB module can generate multiple interrupt
conditions. To accommodate all of these interrupt
sources, the module is provided with its own interrupt
logic structure, similar to that of the microcontroller.
USB interrupts are enabled with one set of control
registers and trapped with a separate set of flag regis-
ters. All sources are funneled into a single USB inter-
rupt
microcontroller’s interrupt logic.
FIGURE 14-8:
FIGURE 14-9:
© 2006 Microchip Technology Inc.
Note
Differential Data
request,
USB Interrupts
1:
UEIR (Flag) and UEIE (Enable) Registers
The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
USB Reset
CRC5EF
CRC5EE
URSTIF
RESET
BTOEE
BTSEE
BTOEF
BTSEF
Second Level USB Interrupts
PIDEF
PIDEE
CRC16EE
CRC16EF
USBIF
DFN8EE
DFN8EF
START-OF-FRAME
(USB Error Conditions)
USB INTERRUPT LOGIC FUNNEL
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
SOFIF
SOF
(PIR2<5>),
SETUP
Advance Information
in
DATA
the
STATUS
STALLIE
STALLIF
UERRIE
UERRIF
ACTVIF
ACTVIE
URSTIE
URSTIF
IDLEIF
IDLEIE
SOFIF
SOFIE
TRNIE
TRNIF
Figure 14-8 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction. Figure 14-9 shows some common events
within a USB frame and their corresponding interrupts.
SETUPToken
OUT Token
Control Transfer
UIR (Flag) and UIE (Enable) Registers
From Host
IN Token
From Host
From Host
Top Level USB Interrupts
(USB Status Interrupts)
PIC18F2450/4450
Empty Data
Transaction
From Host
From Host
To Host
(1)
Data
Data
From Host
To Host
To Host
ACK
ACK
ACK
SOF
USBIF
1 ms Frame
DS39760A-page 143
Transaction
Set TRNIF
Set TRNIF
Set TRNIF
Complete