PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 212

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PIC18F2455-I/SP

Manufacturer Part Number
PIC18F2455-I/SP
Description
Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F2455-I/SP

A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
23
Interface
I2C/SPI/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
24K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2455-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F2450/4450
Even when the dedicated port is enabled, the ICSP and
ICD functions remain available through the legacy port.
When V
of the ICRST/ICV
18.9.2
PIC18F4450 devices in 44-pin TQFP packages also
have the ability to change their configuration under
external control for debugging purposes. This allows
the device to behave as if it were a PIC18F2455/2550
28-pin device.
This 28-pin Configuration mode is controlled through a
single pin, NC/ICPORTS. Connecting this pin to V
forces the device to function as a 28-pin device.
Features normally associated with the 40/44-pin
devices are disabled, along with their corresponding
control registers and bits. On the other hand,
connecting the pin to V
in its default configuration.
The configuration option is only available when
background debugging and the dedicated ICD/ICSP
port are both enabled (DEBUG Configuration bit is
clear and ICPRT Configuration bit is set). When
disabled, NC/ICPORTS is a No Connect pin.
18.10 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply
ICSP Programming (formerly known as Low-Voltage
ICSP Programming or LVP) . When Single-Supply
Programming is enabled, the microcontroller can be
programmed without requiring high voltage being
applied to the MCLR/V
PGM pin is then dedicated to controlling Program
mode entry and is not available as a general purpose
I/O pin.
While programming using Single-Supply Program-
ming, V
normal execution mode. To enter Programming mode,
V
DS39760A-page 210
DD
Note 1: The ICPRT Configuration bit can only be
is applied to the PGM pin.
IH
DD
2: The ICPRT Configuration bit must be
is seen on the MCLR/V
is applied to the MCLR/V
28-PIN EMULATION
programmed through the default ICSP
port.
maintained clear for all 28-pin and 40-pin
devices; otherwise, unexpected operation
may occur.
PP
pin is ignored.
DD
PP
/RE3 pin, but the RB5/KBI1/
forces the device to function
PP
/RE3 pin, the state
PP
/RE3 pin as in
Advance Information
SS
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RB5/KBI1/PGM then
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (V
V
standard high-voltage programming is available and
must be used to program the device.
Memory that is not code-protected can be erased using
either a Block Erase, or erased row by row, then written
at any specified V
erased, a Block Erase is required. If a Block Erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with V
PP
Note 1: High-Voltage Programming is always
/RE3 pin). Once LVP has been disabled, only the
2: While in Low-Voltage ICSP Programming
3: When using Low-Voltage ICSP Program-
4: If the device Master Clear is disabled,
available, regardless of the state of the
LVP bit, by applying V
mode, the RB5 pin can no longer be used
as a general purpose I/O pin and should
be held low during normal operation.
ming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low-Voltage Programming
b) make certain that RB5/KBI1/PGM
(CONFIG4L<2> = 0); or
is held low during entry into ICSP.
DD
. If code-protected memory is to be
© 2006 Microchip Technology Inc.
IHH
applied to the MCLR/
IHH
DD
to the MCLR pin.
of 4.5V to 5.5V.

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