PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 130

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2455-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 24K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2450/4450
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 13-3:
TABLE 13-3:
TABLE 13-4:
DS39760A-page 128
INTCON
RCON
PIR1
PIE1
IPR1
TRISC
TMR2
PR2
T2CON
CCPR1L
CCPR1H
CCP1CON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1:
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
Note:
Name
PWM Resolution (max)
PWM Frequency
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
Timer2 Register
Timer2 Period Register
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
GIE/GIEH PEIE/GIEL
TRISC7
IPEN
Bit 7
—
—
—
—
—
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
REGISTERS ASSOCIATED WITH PWM AND TIMER2
SBOREN
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
TRISC6
ADIE
ADIP
ADIF
Bit 6
—
=
log
-----------------------------bits
(1)
2.44 kHz
log
⎛
⎝
---------------
F
F
FFh
PWM
16
10
OSC
TMR0IE
2
DC1B1
RCIF
RCIE
RCIP
Bit 5
—
—
⎞
⎠
Advance Information
9.77 kHz
FFh
INT0IE
DC1B0
10
4
Bit 4
TXIF
TXIE
TXIP
RI
—
39.06 kHz
CCP1M3
13.4.3
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
RBIE
Bit 3
FFh
TO
10
—
—
—
—
1
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Make the CCP1 pin an output by clearing the
appropriate TRIS bit.
Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
Configure the CCP module for PWM operation.
SETUP FOR PWM OPERATION
CCP1M2
TMR0IF
CCP1IE
CCP1IP
CCP1IF
TRISC2
156.25 kHz
Bit 2
PD
3Fh
1
8
© 2006 Microchip Technology Inc.
CCP1M1
TMR2IE
TMR2IP
TMR2IF
TRISC1
INT0IF
Bit 1
POR
312.50 kHz
1Fh
1
7
CCP1M0
TMR1IE
TMR1IP
TMR1IF
TRISC0
Bit 0
RBIF
BOR
416.67 kHz
6.58
17h
1
on page
Values
Reset
49
50
51
51
51
51
50
50
50
50
50
50