PIC24HJ32GP202-I/SO Microchip Technology Inc., PIC24HJ32GP202-I/SO Datasheet - Page 127

• Manufacturer Part Number: PIC24HJ32GP202-I/SO
• Description: 16-BIT MCU, 28LD, 32KB FLASH, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ32GP202-I/SO

• A/d Inputs: 10 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin SOIC
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.0
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices support up to eight input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
• Simple Capture Event modes:
• Capture timer value on every edge (rising and
FIGURE 12-1:
© 2007 Microchip Technology Inc.
Note:
- Capture timer value on every falling edge of
- Capture timer value on every rising edge of
falling)
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
ICx Pin
input at ICx pin
input at ICx pin
INPUT CAPTURE
This data sheet summarizes the features
of
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
PIC24HJ32GP202/204 and PIC24HJ16GP304
Prescaler
(1, 4, 16)
the
Counter
3
INPUT CAPTURE BLOCK DIAGRAM
System Bus
PIC24HJ32GP202/204
ICxCON
ICM<2:0> (ICxCON<2:0>)
ICOV, ICBNE (ICxCON<4:3>)
Mode Select
Edge Detection Logic
Clock Synchronizer
ICxI<1:0>
and
and
Preliminary
(in IFSn Register)
Set Flag ICxIF
Interrupt
Logic
• Prescaler Capture Event modes:
Each input capture channel can select one of the
two 16-bit timers (Timer2 or Timer3) for the time
base. The selected timer can use either an internal
or external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• Four-word FIFO buffer for capture values
• Use of input capture to provide additional sources
- Capture timer value on every 4th rising edge
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
of external interrupts
-Capture timer value on every 16th rising
of input at ICx pin
4 buffer locations are filled
edge of input at ICx pin
Logic
FIFO
R/W
From 16-bit Timers
TMR2 TMR3
1
ICxBUF
16
DS-70289A-page 125
0
16
ICTMR
(ICxCON<7>)