PIC24HJ32GP202-I/SO Microchip Technology Inc., PIC24HJ32GP202-I/SO Datasheet - Page 68
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PIC24HJ32GP202-I/SO
Manufacturer Part Number
PIC24HJ32GP202-I/SO
Description
16-BIT MCU, 28LD, 32KB FLASH, 40 MIPS, NANOWATT
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC24HJ32GP202-ISO.pdf
(244 pages)
Specifications of PIC24HJ32GP202-I/SO
A/d Inputs
10 Channel, 12-Bit
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/UART
Memory Type
Flash
Number Of Bits
16
Package Type
28-pin SOIC
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
3-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-8:
DS70289A-page 66
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-4
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
R/W-0
T2IE
U-0
—
Unimplemented: Read as ‘0’
AD1IE: ADC1 Conversion Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
SPI1IE: SPI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
SPI1EIE: SPI1 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
T3IE: Timer3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC2IE
R/W-0
U-0
—
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
W = Writable bit
‘1’ = Bit is set
AD1IE
R/W-0
R/W-0
IC2IE
U1TXIE
R/W-0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U1RXIE
R/W-0
R/W-0
T1IE
SPI1IE
OC1IE
R/W-0
R/W-0
© 2007 Microchip Technology Inc.
x = Bit is unknown
SPI1EIE
R/W-0
R/W-0
IC1IE
INT0IE
R/W-0
R/W-0
T3IE
bit 8
bit 0
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