PIC24HJ32GP202-I/SO Microchip Technology Inc., PIC24HJ32GP202-I/SO Datasheet - Page 158

• Manufacturer Part Number: PIC24HJ32GP202-I/SO
• Description: 16-BIT MCU, 28LD, 32KB FLASH, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ32GP202-I/SO

• A/d Inputs: 10 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin SOIC
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 16-2:
DS70289A-page 156
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15,13
bit 14
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
bit 5
Note 1:
UTXISEL1
R/W-0
R/W-0
URXISEL<1:0>
Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is
UTXINV: IrDA Encoder Transmit Polarity Inversion bit
1 = IrDA encoded, UxTX Idle state is ‘1’
0 = IrDA encoded, UxTX Idle state is ‘0’
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
0 = Sync Break transmission disabled or completed
UTXEN: Transmit Enable bit
1 = Transmit enabled, UxTX pin controlled by UARTx
0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.
0 = Address Detect mode disabled
UTXINV
R/W-0
R/W-0
cleared by hardware upon completion
by port.
at least one character open in the transmit buffer)
transmit buffer becomes empty
operations are completed
buffer. Receive buffer has one or more characters.
U
x
STA: UART
(1)
HC = Hardware cleared
W = Writable bit
‘1’ = Bit is set
UTXISEL0
ADDEN
R/W-0
R/W-0
x
STATUS AND CONTROL REGISTER
RIDLE
U-0
R-1
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0 HC
UTXBRK
PERR
R-0
(1)
UTXEN
R/W-0
FERR
R-0
© 2007 Microchip Technology Inc.
x = Bit is unknown
UTXBF
OERR
R/C-0
R-0
URXDA
TRMT
R-1
R-0
bit 8
bit 0