PIC24HJ32GP202-I/SO Microchip Technology Inc., PIC24HJ32GP202-I/SO Datasheet - Page 165

• Manufacturer Part Number: PIC24HJ32GP202-I/SO
• Description: 16-BIT MCU, 28LD, 32KB FLASH, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ32GP202-I/SO

• A/d Inputs: 10 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin SOIC
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 17-1:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9-8
bit 7-5
bit 4
bit 3
R/W-0
ADON
R/W-0
PIC24HJ32GP202/204 and PIC24HJ16GP304
ADON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC is off
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
Unimplemented: Read as ‘0’
AD12B: 10-bit or 12-bit Operation Mode bit
1 = 12-bit, 1-channel ADC operation
0 = 10-bit, 4-channel ADC operation
FORM<1:0>: Data Output Format bits
For 10-bit operation:
11 = Reserved
10 = Reserved
01 = Signed integer (D
00 = Integer (D
For 12-bit operation:
11 = Reserved
10 = Reserved
01 = Signed Integer (D
00 = Integer (D
SSRC<2:0>: Sample Clock Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = Reserved
101 = Reserved
100 = Reserved
011 = Reserved
010 = GP timer 3 compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing sample bit ends sampling and starts conversion
Unimplemented: Read as ‘0’
SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> = 01 or 1x)
When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’
1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or
0 = Samples multiple channels individually in sequence
SSRC<2:0>
R/W-0
Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)
U-0
—
AD1CON1: ADC1 CONTROL REGISTER 1
HC = Cleared by hardware
W = Writable bit
‘1’ = Bit is set
OUT
OUT
ADSIDL
R/W-0
R/W-0
= 0000 00dd dddd dddd)
= 0000 dddd dddd dddd)
OUT
OUT
= ssss sssd dddd dddd, where s = .NOT.d<9>)
= ssss sddd dddd dddd, where s = .NOT.d<11>)
Preliminary
U-0
U-0
—
—
HS = Set by hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SIMSAM
R/W-0
U-0
—
AD12B
ASAM
R/W-0
R/W-0
x = Bit is unknown
HC,HS
R/W-0
R/W-0
SAMP
FORM<1:0>
DS70289A-page 163
HC, HS
DONE
R/W-0
R/C-0
bit 8
bit 0