PIC24HJ32GP202-I/SO Microchip Technology Inc., PIC24HJ32GP202-I/SO Datasheet - Page 21

• Manufacturer Part Number: PIC24HJ32GP202-I/SO
• Description: 16-BIT MCU, 28LD, 32KB FLASH, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ32GP202-I/SO

• A/d Inputs: 10 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin SOIC
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.0
The PIC24HJ32GP202/204 and PIC24HJ16GP304
architecture features separate program and data mem-
ory spaces and buses. This architecture also allows the
direct access of program memory from the data space
during code execution.
FIGURE 3-1:
© 2007 Microchip Technology Inc.
Note:
MEMORY ORGANIZATION
This data sheet summarizes the features
of
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
PIC24HJ32GP202/204 and PIC24HJ16GP304
PIC24HJ32GP202/204
the
Interrupt Vector Table
Alternate Vector Table
Device Configuration
(11264 instructions)
GOTO Instruction
PROGRAM MEMORY FOR PIC24HJ32GP202/204 AND PIC24HJ16GP304 DEVICES
Unimplemented
Reset Address
Flash Memory
User Program
(Read ‘0’s)
Reserved
DEVID (2)
Registers
Reserved
Reserved
PIC24HJ32GP202/204
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x0057FE
0x005800
0x7FFFFE
0x800000
0xF7FFFE
0xF80000
0xF80017
0xF80018
0xFEFFFE
0xFF0000
0xFFFFFE
and
Preliminary
3.1
The
PIC24HJ32GP202/204
devices is 4M instructions. The space is addressable
by a 24-bit value derived either from the 23-bit Program
Counter (PC) during program execution, or from table
operation or data space remapping as described in
Section 3.4 “Interfacing Program and Data Memory
Spaces”.
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory maps for the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices are shown in Figure 3-1.
program
Program Address Space
Interrupt Vector Table
Alternate Vector Table
Device Configuration
PIC24HJ16GP304
(5632 instructions)
GOTO Instruction
Unimplemented
Reset Address
address
Flash Memory
User Program
(Read ‘0’s)
Reserved
Registers
DEVID (2)
Reserved
Reserved
and
memory
PIC24HJ16GP304
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x002BFE
0x002C00
0x7FFFFE
0x800000
0xF7FFFE
0xF80017
0xF80018
0xFEFFFE
0xFF0000
0xFFFFFE
DS70289A-page 19
0xF80000
space
of
the