PIC24HJ32GP202-I/SO Microchip Technology Inc., PIC24HJ32GP202-I/SO Datasheet - Page 175

• Manufacturer Part Number: PIC24HJ32GP202-I/SO
• Description: 16-BIT MCU, 28LD, 32KB FLASH, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ32GP202-I/SO

• A/d Inputs: 10 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin SOIC
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

18.0
PIC24HJ32GP202/204
devices include several features that are intended to
maximize application flexibility and reliability, and mini-
mize cost through elimination of external components.
These are:
• Flexible configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit emulation
TABLE 18-1:
© 2007 Microchip Technology Inc.
0xF80000
0xF80002
0xF80004
0xF80006
0xF80008
0xF8000A FWDT
0xF8000C FPOR
0xF8000E Reserved
0xF80010
0xF80012
0xF80014
0xF80016
Note 1:
Note:
Address
SPECIAL FEATURES
These reserved bits read as ‘1’ and must be programmed as ‘1’.
This data sheet summarizes the features
of
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FBS
Reserved
FGS
FOSCSEL
FOSC
FUID0
FUID1
FUID2
FUID3
Name
the
DEVICE CONFIGURATION REGISTER MAP
PIC24HJ32GP202/204
FWDTEN
and
IESO
Bit 7
FCKSM<1:0>
—
—
—
PIC24HJ16GP304
WINDIS
Bit 6
—
—
—
—
and
IOL1WAY
Preliminary
Bit 5
—
—
—
—
—
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
18.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The Device Configuration register map is shown in
Table 18-1.
The individual Configuration bit descriptions for the
FBS, FGS, FOSCSEL, FOSC, FWDT, FPOR and FICD
Configuration registers are shown in Table 18-2.
Note that address 0xF80000 is beyond the user pro-
gram memory space. It belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using table reads and table writes.
The upper byte of all device Configuration registers
should always be ‘1111
appear to be NOP instructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’ to these locations
has no effect on device operation.
To prevent the inadvertent configuration changes dur-
ing code execution, all programmable Configuration
bits are write-once. After a bit is initially programmed
during a power cycle, it cannot be written to again.
Changing a device configuration requires that power to
the device be cycled.
WDTPRE
ALTI2C
Reserved
Reserved
Bit 4
—
—
—
Configuration Bits
—
(1)
(1)
Bit 3
—
—
—
BSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
Bit 2
1111.’ This makes them
GSS<1:0>
FPWRT<2:0>
FNOSC<2:0>
DS70289A-page 173
Bit 1
GWRP
BWRP
Bit 0