PIC24HJ32GP202-I/SO Microchip Technology Inc., PIC24HJ32GP202-I/SO Datasheet - Page 36

• Manufacturer Part Number: PIC24HJ32GP202-I/SO
• Description: 16-BIT MCU, 28LD, 32KB FLASH, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ32GP202-I/SO

• A/d Inputs: 10 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin SOIC
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24HJ32GP202/204 and PIC24HJ16GP304
3.2.5
In addition to its use as a working register, the W15
register
PIC24HJ16GP304 devices is also used as a software
Stack Pointer. The Stack Pointer always points to the
first available free word and grows from lower to higher
addresses. It pre-decrements for stack pops and post-
increments for stack pushes, as shown in Figure 3-4.
For a PC push during any CALL instruction, the MSB of
the PC is zero-extended before the push, ensuring that
the MSB is always clear.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. Similarly,
the Stack Pointer, SPLIM<0> is forced to ‘0’ because
all stack operations must be word aligned.
When an EA is generated using W15 as a source or
destination pointer, the resulting address is compared
with the value in SPLIM. If the contents of the Stack
Pointer (W15) and the SPLIM register are equal and a
push operation is performed, a stack error trap will not
occur. The stack error trap will occur on a subsequent
push operation. For example, to cause a stack error
trap when the stack grows beyond address 0x2000 in
RAM, initialize the SPLIM with the value 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be lesser than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-4:
DS70289A-page 34
0x0000
Note:
15
000000000
in
SOFTWARE STACK
A PC push during exception processing
concatenates the SRL register to the MSB
of the PC prior to the push.
<Free Word>
PC<15:0>
the
PC<22:16>
CALL STACK FRAME
PIC24HJ32GP202/204
0
POP : [--W15]
PUSH : [W15++]
W15 (before CALL)
W15 (after CALL)
and
Preliminary
3.2.6
The PIC24H product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot
Segment Flash code when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code when enabled. See
Table 3-1 for an overview of the BSRAM and SSRAM
SFRs.
3.3
The addressing modes shown in Table 3-22 form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of instruc-
tions differ from those in the other instruction types.
3.3.1
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (Near Data Space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
3.3.2
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where, Operand 1 is always a working register (that is,
the addressing mode can only be register direct), which
is referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location.
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
Note:
Instruction Addressing Modes
The
DATA RAM PROTECTION FEATURE
FILE REGISTER INSTRUCTIONS
MCU INSTRUCTIONS
Not all instructions support all the
addressing modes given above. Individual
instructions can support different subsets
of these addressing modes.
following
© 2007 Microchip Technology Inc.
addressing
modes
are