PIC24HJ32GP202-I/SO Microchip Technology Inc., PIC24HJ32GP202-I/SO Datasheet - Page 60
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PIC24HJ32GP202-I/SO
Manufacturer Part Number
PIC24HJ32GP202-I/SO
Description
16-BIT MCU, 28LD, 32KB FLASH, 40 MIPS, NANOWATT
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC24HJ32GP202-ISO.pdf
(244 pages)
Specifications of PIC24HJ32GP202-I/SO
A/d Inputs
10 Channel, 12-Bit
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/UART
Memory Type
Flash
Number Of Bits
16
Package Type
28-pin SOIC
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
3-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-1:
DS70289A-page 58
bit 15
bit 7
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
bit 7-5
Note 1:
R/W-0
IPL2
U-0
—
2:
3:
(2)
(3)
For complete register details, see Register 2-1: “SR: CPU STATUS Register”.
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
R/W-0
IPL1
U-0
—
SR: CPU STATUS REGISTER
(2)
(3)
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
R/W-0
IPL0
U-0
—
(2)
(3)
U-0
R-0
RA
Preliminary
—
(1)
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
R/W-0
U-0
—
N
(1)
R/W-0
U-0
OV
—
© 2007 Microchip Technology Inc.
R/W-0
U-0
—
Z
R/W-0
R/W-0
DC
C
bit 8
bit 0
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