NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet
NCT6627UD
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NCT6627UD Summary of contents
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... W83627UHG NCT6627UD NUVOTON LPC I/O th Date: October 26 , 2010 Revision: 1.7 Publication Release Date: October 26, 2010 -I- Revision 1.7 ...
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TABLE OF CONTENTS – 1. GENERAL DESCRIPTION ......................................................................................................... 1 2. FEATURES ................................................................................................................................. 3 3. BLOCK DIAGRAM ...................................................................................................................... 6 4. PIN LAYOUT............................................................................................................................... 7 5. PIN DESCRIPTION..................................................................................................................... 8 5.1 LPC Interface ........................................................................................................................ 9 5.2 FDC Interface........................................................................................................................ 9 5.3 Multi-Mode Parallel Port...................................................................................................... 11 ...
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Fan Speed Measurement and Control................................................................................ 42 7.6.1 Fan Speed Measurement............................................................................................................42 7.6.2 Fan Speed Control ......................................................................................................................43 TM 7.6.3 SMART FAN Control ...............................................................................................................44 7.7 Interrupt Detection .............................................................................................................. 52 7.7.1 SMI# Interrupt Mode ...................................................................................................................52 7.7.2 OVT# Interrupt Mode ..................................................................................................................55 7.7.3 Caseopen Detection....................................................................................................................55 ...
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SMI# Mask Register 2 – Index 44h (Bank 0) ...................................................................... 71 8.35 Reserved Register – Index 45h (Bank 0).......................................................................... 72 8.36 SMI# Mask Register 3 – Index 46h (Bank 0) ...................................................................... 72 8.37 Fan Divisor Register I – Index ...
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Reserved Registers – Index 52h (Bank 2).......................................................................... 87 8.80 Reserved Registers – Index 53h (Bank 2).......................................................................... 87 8.81 Reserved Registers – Index 54h (Bank 2).......................................................................... 87 8.82 Reserved Registers – Index 55h (Bank 2).......................................................................... 87 8.83 Reserved Registers – ...
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Interrupt Status Register (ISR) (Read only) .............................................................................121 10.2.7 Interrupt Control Register (ICR) (Read/Write)..........................................................................122 11. PARALLEL PORT ................................................................................................................... 124 11.1 Printer Interface Logic....................................................................................................... 124 11.2 Enhanced Parallel Port (EPP)........................................................................................... 124 11.2.1 Data Port (Data Swapper) .......................................................................................................125 11.2.2 Printer Status Buffer ...
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Stop Frame ....................................................................................................................... 153 15. WATCHDOG TIMER............................................................................................................... 154 16. GENERAL PURPOSE I/O....................................................................................................... 155 16.1 GPIO Architecture............................................................................................................. 155 16.2 Access Channels .............................................................................................................. 155 17. CONFIGURATION REGISTER............................................................................................... 157 17.1 Chip (Global) Control Register.......................................................................................... 157 17.2 Logical Device 0 (FDC)..................................................................................................... 165 17.3 ...
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List of Figures Figure 3-1 W83627UHG Block Diagram ........................................................................................... 6 Figure 4-1 W83627UHG Pin Layout ................................................................................................. 7 Figure 6-1 Structure of the Configuration Register ......................................................................... 22 Figure 6-2 Configuration Register ................................................................................................... 24 Figure 7-1 LPC Bus’ Reads from / Writes ...
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List of Tables Table 6-1 Devices of I/O Base Address .......................................................................................... 23 Table 6-2 Chip (Global) Control Registers ...................................................................................... 26 Table 7-1 Temperature Data Format .............................................................................................. 34 Table 7-2 SST Command Summary ............................................................................................... 37 Table 7-3 Typical Temperature Values ........................................................................................... ...
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... These GPIO ports may serve as simple I/O ports or may be individually configured to provide alternative functions. The W83627UHG supports the SST (Simple Serial Transport) interface and Intel Control Interface). The W83627UHG fully complies with the Microsoft© PC98 and PC99 Hardware Design Guide and meets the requirements of ACPI. W83627UHG/NCT6627UD and S ...
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... Please pay attention to the layout of these two power supplies to avoid short circuits. Otherwise, the feature will not function. There is NCT6627UD, which is exactly the same as W83627UHG, except the package dimension. NCT6627UD is thin package type, LQFP-128, 14mm x 14mm body size; W83627UHG is QFP-128, 14mm x 20mm body size. ...
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... Programmable baud rate generator allows division of clock source by any value from -1) Maximum baud rate for clock source 14.769 MHz 921K bps. The baud rate at 24 MHz is 1.5M bps. Support RS485 auto flow control of four UARTs. (UARTA, UARTC, UARTD and UARTE) --- for rev. E only W83627UHG/NCT6627UD Publication Release Date: October 26, 2010 -3- Revision 1.7 ...
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... Dual mode for fan control (PWM and DC) • Built-in case open detection circuit • Programmable hysteresis and setting points for all monitored items • Over-temperature indicator output • Issue SMI#, OVT# to activate system protection TM • Nuvoton Hardware Doctor W83627UHG/NCT6627UD TM firmware F MART III functions MART AN TM ...
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... Support SST 0.9 Specification PECI Interface PECI Host Support PECI 1.0 Specification Support 4 CPU addresses and 2 domains per CPU address Package W83627UHG 128-pin QFP, 14mm x 20mm x 2.75mm NCT6627UD 128-pin LQFP, 14mm x 14mm x 1.4mm Green / RoHS W83627UHG/NCT6627UD Publication Release Date: October 26, 2010 -5- Revision 1.7 ...
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... BLOCK DIAGRAM LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ General GPIO purpose IO PECI interface PECI SST interface SST HM Hardware monitor Keyboard/Mouse KBC Figure 3-1 W83627UHG and NCT6627UD Block Diagram W83627UHG/NCT6627UD LPC Interface Floppy drive FDC UART Serial port A, B,C,D,E IRRX IR IRTX Printer port ...
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... DSRE#/GP56 DSRE#/GP56 126 126 RTSE#/GP55 RTSE#/GP55 127 127 DTRE#/GP54 DTRE#/GP54 128 128 W83627UHG/NCT6627UD 5VCC 5VCC Vtt Vtt VSB VSB VBAT VBAT W83627UHG W83627UHG 5VCC 5VCC Figure 4-1 W83627UHG Pin Layout Publication Release Date: October 26, 2010 ...
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... Open-drain output pin with 12mA sink capability Open-drain output pin with 24mA sink capability Output pin with 8mA source-sink capability Output pin with 12mA source-sink capability Output pin with 24mA source-sink capability 24 W83627UHG/NCT6627UD for details. Publication Release Date: October 26, 2010 -8- Revision 1.7 ...
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... DSRF DSA RTSF# 24 W83627UHG/NCT6627UD DESCRIPTION System clock input, either 24MHz or 48MHz. The actual frequency must be specified in register. The default value is 48MHz. Generated PME event. PCI-clock 33-MHz input. Encoded DMA Request signal. Serialized IRQ input / output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral ...
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... OD HEAD# 24 Logic 1 = side 0 17 Logic 0 = side 1 Ring Indicator. An active low signal indicates that a ring signal IN RIF being received from the modem or data set. W83627UHG/NCT6627UD DESCRIPTION This open-drain output determines which disk Publication Release Date: October 26, 2010 -10- Revision 1.7 ...
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... See the description of the parallel port for the definition of this pin in ECP and EPP modes. W83627UHG/NCT6627UD DESCRIPTION Diskette Change. This signal is active-low at power-on and whenever the diskette is removed. This input pin needs to connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive compatibility ...
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... Clear To Send. This is the modem-control input. The function of IN CTSB# these pins can be tested by reading bit 4 of the handshake status t 78 register. (This is for W83627UHG only) I/OD GP17 General-purpose I/O port 1 bit 7. 12t W83627UHG/NCT6627UD DESCRIPTION See the description of the parallel port DESCRIPTION Publication Release Date: October 26, 2010 -12- Revision 1.7 ...
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... DSRF# data set is ready to establish a communication link and transfer t data to the UART. (This is for W83627UHG only) 7 Motor A On. When set to 0, this pin enables disk drive 0. This is OD MOA open drain output. W83627UHG/NCT6627UD DESCRIPTION Publication Release Date: October 26, 2010 -13- Revision 1.7 ...
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... UART F. UART B Data Terminal Ready. An active-low signal informs the O DTRB# modem or data set that the controller is ready to communicate (This is for W83627UHG only) I/OD GP14 General-purpose I/O port 1 bit 4. 12t W83627UHG/NCT6627UD DESCRIPTION Publication Release Date: October 26, 2010 -14- Revision 1.7 ...
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... Step output pulses. This active low open drain output produces a OD STEP# 24 pulse to move the head to another track. UART A Serial Output. This pin is used to transmit serial data out O SOUTA the communication link. W83627UHG/NCT6627UD DESCRIPTION Publication Release Date: October 26, 2010 -15- Revision 1.7 ...
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... DCDC# t data set has detected a data carrier. 115 I/OD GP31 General-purpose I/O port 3 bit 1. 12t Data Carrier Detect. An active-low signal indicates the modem or IN 123 DCDD# t data set has detected a data carrier. W83627UHG/NCT6627UD DESCRIPTION Publication Release Date: October 26, 2010 -16- Revision 1.7 ...
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... Logic 0 = side 1 5.5 KBC Interface SYMBOL PIN I/O GA20M KBRST W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION Gate A20 output. This pin is high after system reset. (KBC P21) Keyboard reset. This pin is high after system reset. (KBC P20) Publication Release Date: October 26, 2010 -17- Revision 1.7 ...
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... CPUFANOUT SYSFANOUT 92 AOUT OD 108 PLED 12 W83627UHG/NCT6627UD DESCRIPTION Keyboard Clock. Keyboard Data. PS2 Mouse Clock. PS2 Mouse Data. DESCRIPTION Beep function for hardware monitor. This pin is low after system reset. General-purpose I/O port 2 bit 1. CASE OPEN Detection. An active-low input from an external device when the case is open. This signal can be latched if pin VBAT is connected to the battery, even if the W83627UHG is turned off ...
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... I/OD SDA 12t 69 I/OD GP26 12t 5.10 General Purpose I/O Port 5.10.1 GPIO Power Source SYMBOL W83627UHG/NCT6627UD DESCRIPTION General-purpose I/O port 2 bit 0. DESCRIPTION ® INTEL CPU PECI interface. Connect to CPU. ® INTEL CPU Vtt Power. DESCRIPTION Simple Serial Transport (SST) Interface. ...
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... GPIO-3 Interface See 5.4 Serial Port & Infrared Port Interface 5.10.5 GPIO-4 Interface See 5.4 Serial Port & Infrared Port Interface 5.10.6 GPIO-5 Interface W83627UHG/NCT6627UD POWER SOURCE 5VSB 5VCC 5VCC 5VCC 5VCC 5VCC DESCRIPTION Publication Release Date: October 26, 2010 -20- ...
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... AVCC 97 AGND 105 20,55 VSS Vtt 89 W83627UHG/NCT6627UD DESCRIPTION Watchdog timer output signal. Suspend-LED output signal. This pin is low as default. DESCRIPTION +5 V stand-by power supply for the digital circuit on-board battery for the digital circuit power supply for the digital circuit. +3.3V power supply for driving 3V on the host interface. ...
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... Logical Device Logical Device Logical Device Logical Device Configuration Configuration Configuration Configuration # Figure 6-1 Structure of the Configuration Register W83627UHG/NCT6627UD One Per One Per One Per One Per Logical Device Logical Device Logical Device Logical Device # Publication Release Date: October 26, 2010 -22- Revision 1.7 ...
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... Keyboard Controller WDTO# & PLED, and GPIO Hardware Monitor C PECI & SST UART F (This is for W83627UHG W83627UHG/NCT6627UD I/O BASE ADDRESS FDC 100h ~ FF8h 100h ~ FF8h UART A 100h ~ FF8h 100h ~ FF8h only) Reserved 100h ~ FF8h UART C 100h ~ FF8h GPIO 3, 4 100h ~ FF8h ...
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... Enter the Extended Function Mode To place the chip into the Extended Function Mode, two successive writes of 0x87 must be applied to Extended Function Enable Registers (EFERs, i.e. 2Eh or 4Eh). W83627UHG/NCT6627UD Any other I/O transition cycle Any other I/O transition cycle I/O Write to 2Eh ...
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... MOV DX, 2EH MOV AL, 87H OUT DX, AL OUT DX, AL ;----------------------------------------------------------------------------- ; Configure Logical Device 1, Configuration Register CRF0 ;----------------------------------------------------------------------------- MOV DX, 2EH MOV AL, 07H OUT DX point to Logical Device Number Reg. MOV DX, 2FH MOV AL, 01H OUT DX select Logical Device 1 ; W83627UHG/NCT6627UD Publication Release Date: October 26, 2010 -25- Revision 1.7 ...
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... R/W 29h R/W 2Ah R/W 2Bh 2Ch R/W 2Dh R/W 2Eh R/W 2Fh R/W S: Strapping; x: chip version. W83627UHG/NCT6627UD DEFAULT VALUE DESCRIPTION Software Reset 00h Logical Device A2h Chip ID, MSB 3xh Chip ID, LSB FFh Device Power Down F0h Device Power Down 0100_0ss0b ...
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... W83627UHG can generate pop-up warnings or beep tones when a parameter goes outside of a user-specified range. The rest of this section introduces the various features of the W83627UHG hardware-monitor capability. These features are divided into the following sections: • Access Interfaces W83627UHG/NCT6627UD BIOS. In addition, the Publication Release Date: October 26, 2010 -27- C interface and Revision 1 ...
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... Chapter 6. Due to the number of internal registers necessary to separate the register sets into “banks” specified by register 4Eh. The structure of the internal registers is shown in the following figure. W83627UHG/NCT6627UD 2 C, for the microprocessor to read or write the internal Publication Release Date: October 26, 2010 -28- Revision 1 ...
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... LPC Bus Port 5h Index Register Port 6h Data Register Figure 7-1 LPC Bus’ Reads from / Writes to Internal Registers W83627UHG/NCT6627UD Smart Fan Configuration Registers 00h-1Fh Monitor Value Registers 20h~3Fh Configuration Register 40h Interrupt Status Registers 41h, 42h SMI# Mask Registers 43h, 44h, 46h ...
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... Start By Master Frame 1 Serial Bus Address Byte SCL (Continued) SDA (Continued) Figure 7-2 Serial Bus Write to Internal Address Register Followed by the Data Byte W83627UHG/NCT6627UD 2 C specification, allowing external components that are 2 C interface to write to an internal register and how R/W ...
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... Serial bus read from a register 0 SCL SDA Start By Master Frame 1 Serial Bus Address Byte Frame 3 Repeat start Serial Bus Address Byte by Master Figure 7-3 Serial Bus Read from Internal Address Register W83627UHG/NCT6627UD R Ack by Frame 2 627UHG Internal Index Register Byte R Ack Frame 4 ...
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... Figure 7-4 Analog Inputs and Application Circuit of the W83627UHG As illustrated in the figure above, other connections may require some external circuits. The rest of this section provides more information about voltages outside the range of the 8-bit ADC, CPU Vcore voltage detection, and temperature measurement W83627UHG/NCT6627UD Pin 97 AVCC Pin 74 ...
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... R3 and R4 can be set to 120 KΩ and 10 KΩ, respectively, to reduce negative input voltage V than 2.048 V. Note that R4 is referenced to VREF, or 2.048V instead allow for more dynamic range. This is simply good analog practice to yield the most precise measurements. W83627UHG/NCT6627UD (+12 V) should be reduced before it is connected to VIN0 0 ...
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... External thermistors should have a β value of 3435K and a resistance of 10 KΩ at 25°C. As illustrated in the schematic below, the thermistor is connected in series with a 10-KΩ resistor and then connects to VREF (pin 102). W83627UHG/NCT6627UD Detected Voltage = Reading * 0.008 V Table 7-1 Temperature Data Format ...
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... The configuration registers to select a thermal diode temperature sensor and the measurement method are found at Bank 0, Index 59h, 5Dh, and 5Eh. D+ Thermal Diode D- Figure 7-6 Monitoring Temperature from Thermal Diode (Voltage Mode) W83627UHG/NCT6627UD R 10K, 1% VREF Pin 102 CPUTIN Pin 103 ...
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... The reference voltage is integrated and fixed with the 8-bit ADC, yielding a maximum voltage on each of 2.048V and an LSB of 8mV. As discussed in the previous section 7.3, voltage scaling using resistive dividers may be necessary to keep external voltages within the maximum input voltage range. The power supply pins have integrated resistive dividers. W83627UHG/NCT6627UD W83627UHG CPUTIN (SYSTIN) ...
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... GetExtTemp() GetAllTemps() GetVolt12V() GetVolt5V() GetVolt3p3V() GetVolt2p5V() GetVoltVccp() GetAllVoltages() W83627UHG/NCT6627UD Table 7-2 SST Command Summary DESCRIPTION This command is used to recover from serious hardware or bus error. Support 8-byte and 16-byte read length Returns the 20byte temperature data values for pin SYSTIN (Pin 104) ...
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... VIN0 (pin 100) is connected as shown below: +12V R1 150K 1% 4) “+3VCC” = Decimal[2-byte data by GetVolt3p3V()] / 1024 / ((R3+R4) / R4) volts VIN1 (pin 99) is connected as shown below: W83627UHG/NCT6627UD Table 7-3 Typical Temperature Values 16-BIT DIGITAL OUTPUT (2’S COMPLEMENT) 16-BIT BINARY 0001 0100 0000 0000 0001 0011 1110 0000 ...
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... Program Logical Device C, CR[E0h] bit (7..4) for each PECI Agent. Setting to “1” enables the W83627UHG to access the agent. The power-on default is disabled. After an agent is enabled, the W83627UHG issues PING and GetTemp commands to obtain the PECI temperature. W83627UHG/NCT6627UD VIN1 1 AGND ...
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... In addition, each PECI Agent relative temperature can be read in Logical Device C, CR[E0h] ~ CR[E7h], as long as Logical Device C, CR[E8h] bit 3 is set to “1”. When this bit is “1”, Logical Device C, CR[E0h] ~ CR[E7h] become “Read Only” registers. W83627UHG/NCT6627UD Publication Release Date: October 26, 2010 -40- ...
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... A warning flag register at Logical Device C, CR[E8h] bit (7..4) is designed for each PECI Agent to report whether the W83627UHG (PECI host) detects the PECI client or not and whether the PECI client returns invalid FCS values from the polling for three successive times. W83627UHG/NCT6627UD CPU PECI ...
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... The following table provides some examples of the relationship between divisor, RPM, and count. Table 7-5 Divisor, RPM, and Count Relation NOMINAL DIVISOR RPM 1 8800 4400 2 (default) 4 2200 8 1100 16 550 W83627UHG/NCT6627UD × RPM × Count Divisor Table 7-4 Fan Divisor Definition FAN DIVISOR BIT 2 BIT 1 ...
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... For DC, the W83627UHG has a six bit digital-to-analog converter (DAC) that produces Volts DC. The analog output is programmed at Bank0 Index 01h and Index 03h. The analog output can be calculated using the following equation: OUTPUT Voltage (V) The default value is 111111YY, or nearly 5 V, and reserved bit. W83627UHG/NCT6627UD TIME PER COUNTS REVOLUTION 218.16 ms 153 436 ...
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... If the temperature still exceeds the high end, fan output increases slowly. If the fan is operating at full speed but the temperature still exceeds the high end, a warning message is issued to protect the system. (2) If the temperature falls below the high end (e.g., 58 °C) but remains above the low end (e.g., 52 °C), fan output remains the same. W83627UHG/NCT6627UD features— ...
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... The following figures illustrate two examples of Thermal Cruise Figure 7-10 Mechanism of Thermal Cruise Figure 7-11 Mechanism of Thermal Cruise W83627UHG/NCT6627UD TM mode. TM Mode (PWM Duty Cycle) TM ...
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... Bank1, Index Current CPU Temperature 50h ,51h Bank0, Index Current SYS Temperature 27h Current Bank0, Index CPUFANOUT 03h Output Value Current Bank0 Index SYSFANOUT 01h W83627UHG/NCT6627UD TM mode Mode MART AN REGISTER NAME ATTRIBUTE CPUTIN Temperature Read only Sensor SYSTIN Temperature Read only ...
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... III controls the fan speed so that the temperature meets the target temperature set in BIOS or MART AN application software. There is only one pair of fan outputs and temperature sensors in S • CPUFANOUT and the temperature sensor selected by Bank0 Index 49h, bits W83627UHG/NCT6627UD REGISTER NAME ATTRIBUTE KEEP MIN. START- ...
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... If the current temperature is higher than (Target Temperature + Temperature Tolerance), fan speed rises one step. The step is the value in the CPUFANOUT Output Value Select Register, Bank0, Index 03h. In addition, the target temperature shifts to (Target Temperature + Temperature Tolerance), creating a new target temperature, named Target Temperature 1 in this figure. W83627UHG/NCT6627UD Pin 90 CPUFANOUT Setting ...
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... The step is the value in the CPUFANOUT Output Value Select Register, Bank0, Index 03h. In addition, the target temperature shifts to (Target Temperature － Temperature Tolerance), creating a new target temperature named Target Temperature 1.This is illustrated in the figure below. W83627UHG/NCT6627UD Tolerance Tolerance Tar 1 ...
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... Table 7-9 Display Register – REGISTER DESCRIPTION ADDRESS Bank1, Index Current CPU Temperature 50h ,51h Current Bank0, Index CPUFANOUT 03h Output Value W83627UHG/NCT6627UD Tolerance Tolerance Tar Tar Tar 2 Tar 2 Tar 3 Tar 3 Tar 1 Tar III Mechanism (Current Temp. < Target Temp. – Tol.) ...
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... MART AN MODE TEMPERATURE Bank0, Index CPUFANOUT 06h III MART AN OUTPUT STEP MODE Bank0, Index CPUFANOUT 68h W83627UHG/NCT6627UD TM F III Control Mode MART AN STOP VALUE MAX. FAN TOLERANCE (MIN. FAN OUTPUT OUTPUT) Bank0, Index Bank0, Bank0, Index 07h, bit 4-7 Index 09h 67h KEEP MIN ...
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... SYSTIN and the other for CPUTIN. 7.7.1.3.1. Temperature Sensor 1(SYSTIN) SMI# Interrupt The SMI# pin has three interrupt modes with SYSTIN. 5. Comparator Interrupt Mode This mode is enabled by setting T W83627UHG/NCT6627UD Fan Count limit SMI (Temperature Hysteresis) to 127° ...
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... In this mode, the SMI# pin can create an interrupt when the current temperature rises above T temperature rises above T , however, and generates an interrupt, this mode does not generate additional O interrupts, even if the temperature remains above T must be reset by reading all the interrupt status registers, or subsequent events do not generate interrupts. This is illustrated in the following figure. W83627UHG/NCT6627UD HYST SMI# * ...
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... This is illustrated in the figure below HYST SMI (2) Two-Times Interrupt Mode This mode is enabled by setting Bank0 Index 4Ch, bit 6, to zero. W83627UHG/NCT6627UD OI * *Interrupt Reset when Interrupt Status Registers are read Figure 7-19 SMI Mode of SYSTIN HYST SMI# * ...
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... Caseopen Detection The purpose of Caseopen function is used to detect whether the computer case has been opened and possibly tampered with. This feature must function even when there is no 5VSB power. Consequently, the power source W83627UHG/NCT6627UD . Once the temperature rises above T HYST ...
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... The BEEP alarm function is enabled or disabled by the control bit at Hardware Monitor Device, Bank 0, Index 57h, bit 7. Also, each event has their individual enable bit at Hardware Monitor Device, Bank 0, Index 56h bit[7:0], Index 57h bit[6:0] and Bank 4, Index 53h, bit[1:0]. W83627UHG/NCT6627UD Figure 7-22 Caseopen Mechanism Publication Release Date: October 26, 2010 -56- Revision 1 ...
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... BEEP/GP21 is an open-drain output pin and its default state is low. When the BEEP alarm function is activated, this pin repeatedly outputs 600 Hz square wave for 0.5 second and 1.2 KHz square wave for 0.5 second in turn until the enable bit or the abnormal event is cleared. W83627UHG/NCT6627UD Publication Release Date: October 26, 2010 -57- ...
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... Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT 7 RESERVED. 6-0 READ/WRITE. BIT 7 Reserved ADDRESS 0 DEFAULT 8.2 Data Port (Port x6h) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT W83627UHG/NCT6627UD DATA DESCRIPTION 00h (Address Pointer DATA Publication Release Date: October 26, 2010 -58 ...
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... The maximum value of the divider is 127 (7Fh), and it should not be set to 0. 8.4 SYSFANOUT Output Value Select Register – Index 01h (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME DEFAULT FUNCTION MODE PWM Output (Bank 0, Index DESCRIPTION W83627UHG/NCT6627UD DESCRIPTION PWM_SCALE1 DESCRIPTION Input Clock = Pre_Scale 5 4 ...
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... The clock source is 180 KHz. 6-0 PWM_SCALE2 (CPUFANOUT PWM Pre-Scale Divider). The clock source for PWM output is divided by this seven-bit value to calculate the actual PWM output frequency. PWM output frequency = The maximum value of the divider is 127 (7Fh), and it should not be set to 0. W83627UHG/NCT6627UD creates a duty cycle of 0% ...
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... BIT 7-6 RESERVED. 5-4 CPUFANOUT_MODE. CPUFANOUT mode control. Bits CPUFANOUT is in Manual Mode. (Default CPUFANOUT is in Thermal Cruise 1 0: CPUFANOUT is in Fan Speed Cruise 1 1: CPUFANOUT W83627UHG/NCT6627UD CPUFANOUT0 Value Strap by FAN_SET (Pin 119 CPUFANOUT PWM Duty. The PWM duty cycle is equal to this 8-bit value, divided by 255, times 100% ...
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... CPUTIN Target Temperature Register/ CPUFANIN Target Speed Register – Index 06h (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME CPUTIN Target Temperature / CPUFANIN Target Speed 0 0 DEFAULT FUNCTION MODE TM Thermal Cruise DESCRIPTION MART AN W83627UHG/NCT6627UD DESCRIPTION TM Mode. TM Mode Reserved SYSTIN Target Temperature SYSFANIN Target Speed ...
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... Please note that Stop Value does not mean that fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimum value, and this is Stop Value. 8.12 CPUFANOUT Stop Value Register – Index 09h (Bank 0) Attribute: Read/Write Size: 8 bits W83627UHG/NCT6627UD ...
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... Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT TM In Thermal Cruise mode, CPUFANOUT value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan. W83627UHG/NCT6627UD CPUFANOUT Stop Value III mode, the CPUFANOUT value decreases to this eight-bit value if AN ...
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... The units are intervals of 0.1 seconds. The default time is 6 seconds. (2)For DC output: The units are intervals of 0.4 seconds. The default time is 24 seconds. 8.17 Fan Output Step Down Time Register – Index 0Eh (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT W83627UHG/NCT6627UD SYSFANOUT Stop Time CPUFANOUT Stop Time ...
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... BIT NAME RESERVED. SYSFANOUT_MIN_VALUE 0 0 DEFAULT BIT 7-6 RESERVED. 5 SYSFANOUT_MIN_VALUE. 0: SYSFANOUT value decreases to zero when the temperature goes below the target range. 1: SYSFANOUT value decreases to the value specified in Index 08h when the W83627UHG/NCT6627UD FANOUT Value Step Up Time CPUFANOUT_MIN_VALUE 0 0 DESCRIPTION Publication Release Date: October 26, 2010 ...
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... DEFAULT BIT 7 RESERVED. 6 DIS_OVT1. 0: Enable SYSTIN OVT# output. 1: Disable temperature sensor SYSTIN over-temperature (OVT#) output. 5 RESERVED. 4 OVT1_MODE Compare Mode. (Default) 1: Interrupt Mode. 3-0 RESERVED. 8.28 Reserved Registers – Index 19h ~ 1Fh (Bank 0) W83627UHG/NCT6627UD DESCRIPTION RESERVED OVT1_MODE DESCRIPTION -67 RESERVED Publication Release Date: October 26, 2010 ...
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... Reserved 39h SYSTIN temperature sensor High Limit 3Ah SYSTIN temperature sensor Hysteresis Limit SYSFANIN Fan Count Limit 3Bh Note the number of counts of the internal clock for the Low Limit of the fan speed. W83627UHG/NCT6627UD DESCRIPTION Publication Release Date: October 26, 2010 -68- Revision 1.7 ...
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... SMI#ENABLE. A one enables the SMI# Interrupt output. 0 START. A one enables startup of monitoring operations. A zero puts the part in standby mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike “INT_Clear’’ bit. W83627UHG/NCT6627UD DESCRIPTION ...
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... Thermal Cruise 5 RESERVED. 4 CASEOPEN. A one indicates that the case has been opened. 3 RESERVED. 2 VIN2. A one indicates the high or low limit of VIN2 has been exceeded. 1 RESERVED. 0 VIN1. A one indicates the high or low limit of VIN1 has been exceeded. W83627UHG/NCT6627UD CPUTIN SYSTIN 5VCC AVCC ...
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... TAR1 TAR2 RESERVED 1 1 DEFAULT BIT 7 TAR2 6 TAR1 5 RESERVED 4 CASEOPEN 3-2 RESERVED 1 VIN2 0 VIN1 W83627UHG/NCT6627UD AVCC CPUTIN SYSTIN 5VCC (PIN 97 DESCRIPTION A one disables the corresponding interrupt status bit for the SMI interrupt. (See Interrupt Status Register 1 – Index 41h (Bank 0)). 5 4 ...
Page 81
... CPUFANIN CIV_B0 (CPUFANIN Divisor). 5 SYSFANIN DIV_B1 (SYSFANIN Divisor). 4 SYSFANIN DIV_B0 (SYSFANIN Divisor). 3-0 RESERVED. 8.38 Serial Bus Address Register – Index 48h (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME RESERVED 0 0 DEFAULT W83627UHG/NCT6627UD RESERVED DESCRIPTION SYFANIN SYSFANIN DIV_B1 DIV_B0 DESCRIPTION ...
Page 82
... DEFAULT BIT 7-3 RESERVED. 2 CPUFANOUT TEMP_SEL[2]. 1 CPUFANOUT TEMP_SEL[1]. 0 CPUFANOUT TEMP_SEL[0]. 8.40 SYSFANOUT monitor Temperature source select register – Index 4Ah (Bank 0) Attribute: Read/Write Size: 8 bits W83627UHG/NCT6627UD DESCRIPTION CPUFANOUT CPUFANOUT TEMP_SEL[2] TEMP_SEL[ DESCRIPTION CPUFANOUT Temperature Source Select. Bits Select CPUTIN as CPUFANOUT Monitor Source. ...
Page 83
... Fan Divisor Register II – Index 4Bh (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME RESERVED 0 1 DEFAULT BIT 7-6 RESERVED. W83627UHG/NCT6627UD SYSFANOUT RESERVED TEMP_SEL[ DESCRIPTION SYSFANOUT Temperature Source Select. Bits Select SYSTIN as SYSFANOUT monitor source. (Default Select CPUTIN as SYSFANOUT monitor source. ...
Page 84
... Disable temperature sensor CPUTIN over-temperature (OVT) output. 0: Enable CPUTIN OVT output through pin OVT#. (Default) 2 OVTPOL (Over-temperature polarity). 1: OVT# is active high. 0: OVT# is active low. (Default) 1-0 RESERVED. 8.43 FAN IN/OUT Control Register – Index 4Dh (Bank 0) Attribute: Read/Write W83627UHG/NCT6627UD DESCRIPTION EN_T1_ONE RESERVED DIS_OVT2 ...
Page 85
... Pin 113 (SYSFANIN) generates a logic-high signal. 0: Pin 113 generates a logic-low signal. (Default) 0 FANINC1 (SYSFANIN Input Control). 1: Pin 113 (SYSFANIN) acts as a FAN tachometer input. (Default) 0: Pin 113 acts as a FAN control signal, and the output value is set by bit 1. W83627UHG/NCT6627UD FANOPV2 FANINC2 ...
Page 86
... Attribute: Read Only Size: 16 bits 15 14 BIT NAME 0 1 DEFAULT 7 6 BIT NAME 1 0 DEFAULT BIT 15-8 Vendor ID High-Byte, if Index 4Eh, bit7 is 1. Default 5Ch. 7-0 Vendor ID Low Byte, if Index 4Eh, bit Default A3h. W83627UHG/NCT6627UD RESERVED BANKSEL2 DESCRIPTION VIDL ...
Page 87
... EN_AVCC_BP. BEEP output control for AVCC if the monitored value exceeds the limit. 1 EN_VIN0_BP. BEEP output control for VIN0 if the monitored value exceeds the limit. 0 EN_CPUVCORE_BP. BEEP output control for CPUVCORE if the monitored value exceeds the limit. W83627UHG/NCT6627UD EN_ EN_ EN_ EN_ CPUTIN SYSTIN ...
Page 88
... Enable BEEP output. 0: Disable BEEP output. (Default) 8.49 Chip ID – Index 58h (Bank 0) Attribute: Read Only Size: 8 bits 7 6 BIT NAME 1 1 DEFAULT BIT 7-0 Nuvoton Chip ID Number. Default C1h. 8.50 Reserved Register – Index 59h (Bank 0) W83627UHG/NCT6627UD EN_CASEOPEN_BP RESERVED DESCRIPTION CHIPID ...
Page 89
... VBAT reading value register. 0: Disable battery voltage monitor. Fan divisor table: BIT 2 BIT 1 BIT 0 FAN DIVISOR 8.53 Critical Temperature enable register – Index 5Eh (Bank 0) Attribute: Read/Write Size: 8 bits BIT W83627UHG/NCT6627UD SYSFANIN RESERVED DIODES2 DIV_B2 DESCRIPTION BIT 2 BIT 1 BIT ...
Page 90
... Reserved Registers – Index 60h (Bank 0) 8.56 Reserved Registers – Index 61h (Bank 0) 8.57 Reserved Registers – Index 62h (Bank 0) 8.58 Reserved Registers – Index 63h (Bank 0) 8.59 Reserved Registers – Index 64h (Bank 0) 8.60 Reserved Registers – Index 65h (Bank 0) W83627UHG/NCT6627UD EN_CPUTIN EN_SYSFANOUT ...
Page 91
... Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 1 1 DEFAULT III mode, the CPUFANOUT value increases to this value. This value cannot be zero, and it MART AN cannot be lower than the CPUFANOUT Stop value. W83627UHG/NCT6627UD CPUFANOUT Max. Value Publication Release Date: October 26, 2010 -82 Revision 1.7 ...
Page 92
... Size: 8 bits 7 6 BIT NAME 1 1 DEFAULT TM In Thermal Cruise mode, when CPUFANOUT critical temperature is enabled and monitor temperature over the critical temperature then CPUFANOUT will full drive. 8.68 Reserved Registers – Index 6Dh (Bank 0) W83627UHG/NCT6627UD CPUFANOUT STEP SYSFANOUT CRITICAL TEMPERATURE ...
Page 93
... See CPUFANOUT monitor Temperature source select register – Index 49h(Bank 0) ) 8.72 CPUTIN Configuration Register – Index 52h (Bank 1) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME RESERVED 0 0 DEFAULT BIT 7-5 RESERVED. These bits should be set to 0. W83627UHG/NCT6627UD TEMP<8:1> DESCRIPTION RESERVED DESCRIPTION ...
Page 94
... CPUTIN Hysteresis (Low Byte) Register – Index 54h (Bank 1) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME THYST<0> DEFAULT BIT 7 THYST<0>. Hysteresis temperature bit 0. The nine-bit value is in units of 0.5 6-0 RESERVED. 8.75 CPUTIN Over-temperature (High Byte) Register – Index 55h (Bank1) Attribute: Read/Write W83627UHG/NCT6627UD DESCRIPTION THYST<8:1> DESCRIPTION RESERVED ...
Page 95
... NAME BIT 7-0 TEMP<8:1>. Temperature <8:1> of the SYSTIN/CPUTIN/PECI sensor. The nine-bit value ° units of 0 See SYSFANOUT monitor Temperature source select register – Index 4Ah(Bank 0) ) 8.78 SYSTIN/CPUTIN/PECI Temperature (Low Byte) Register – Index 51h (Bank 2) Attribute: Read Only W83627UHG/NCT6627UD TOVF<8:1> DESCRIPTION ...
Page 96
... BIT 7-2 RESERVED. 1 VBAT. A one indicates the high or low limit of VBAT has been exceeded. 0 5VSB. A one indicates the high or low limit of 5VSB has been exceeded. 8.85 SMI# Mask Register 4 – Index 51h (Bank 4) Attribute: Read/Write Size: 8 bits W83627UHG/NCT6627UD RESERVED DESCRIPTION RESERVED ...
Page 97
... EN_VBAT_BP. BEEP output control for VBAT if the monitored value exceeds the limit. 1: Enable BEEP output. 0: Disable BEEP output. (Default) 0 EN_5VSB_BP. BEEP output control for 5VSB if the monitored value exceeds the limit. 1: Enable BEEP output. 0: Disable BEEP output. (Default) W83627UHG/NCT6627UD RESERVED DESCRIPTION A one disables the corresponding interrupt status bit for the SMI interrupt ...
Page 98
... Reserved Registers – Index 56h (Bank 4) 8.91 Reserved Register – Index 57h-58h (Bank 4) 8.92 Real Time Hardware Status Register I – Index 59h (Bank 4) Attribute: Read Only Size: 8 bits 7 6 BIT CPUFANIN SYSFANIN NAME _STS _STS 0 0 DEFAULT W83627UHG/NCT6627UD OFFSET<7:0> DESCRIPTION OFFSET<7:0> ...
Page 99
... DEFAULT BIT 7 TAR2_STS. Smart Fan of CPUFANIN Warning Status. 1: Selected temperature has been over the target temperature for three minutes at full TM speed in Thermal Cruise 0: Selected temperature has not reached the warning range. 6 TAR1_STS. Smart Fan of SYSFANIN Warning Status. W83627UHG/NCT6627UD DESCRIPTION RESERVED CASEOPEN_STS DESCRIPTION mode ...
Page 100
... VBAT voltage is in the allowed range. 0 5VSB_STS. 5VSB Voltage Status. 1: 5VSB voltage is over or under the allowed range. 0: 5VSB voltage is in the allowed range. 8.95 Reserved Register – Index 5Ch – 5Fh (Bank 4) 8.96 Value RAM 2 ⎯ Index 50h-59h (Bank 5) ADDRESS A6-A0 W83627UHG/NCT6627UD DESCRIPTION mode RESERVED ...
Page 101
... High Limit 55h 5VSB Low Limit 56h VBAT High Limit 57h VBAT Low Limit 58h Reserved 59h Reserved 5Ah Reserved 5Bh Reserved 5Ch Reserved 8.97 Reserved Register – Index 50h – 57h (Bank 6) W83627UHG/NCT6627UD DESCRIPTION Publication Release Date: October 26, 2010 -92- Revision 1.7 ...
Page 102
... Byte FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte W83627UHG/NCT6627UD Table 9-1 The Delays of the FIFO MAXIMUM DELAY UNTIL SERVICING AT 500K BPS Data Rate 1 × 16 μs – 1.5 μs = 14.5 μs 2 × 16 μs – 1.5 μs = 30.5 μs 8 × 16 μs – 1.5 μs = 6.5 μs 15 × ...
Page 103
... Perpendicular mode requires a 1 Mbps data rate for the FDC, and, at this data rate, the FIFO manages the host interface bottleneck due to the high speed of data transfer to and from the disk. 9.1.5 FDC Core W83627UHG/NCT6627UD Publication Release Date: October 26, 2010 -94- ...
Page 104
... Head Unload Time LOCK: Lock EFIFO, FIFOTHR, and PTRTRK bits to prevent being affected by software reset MFM: MFM or FM Mode MT: Multitrack N: The number of data bytes written in a sector NCN: New Cylinder Number ND: Non-DMA Mode W83627UHG/NCT6627UD Publication Release Date: October 26, 2010 -95- Revision 1.7 ...
Page 105
... W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ (2) Read Deleted Data PHASE R Command W MT MFM SK W83627UHG/NCT6627UD HDS DS1 DS0 -96- REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after ...
Page 106
... R/W Command W 0 MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- W83627UHG/NCT6627UD HDS DS1 DS0 HDS DS1 DS0 -97- REMARKS Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution ...
Page 107
... R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ 8. Verify PHASE R Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- -------------------- DTL/SC ------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- W83627UHG/NCT6627UD HDS DS1 DS0 HDS DS1 DS0 -98- REMARKS Sector ID information after command execution REMARKS Command codes The first correct ID ...
Page 108
... 10. Write Data PHASE R Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ (8) Write Deleted Data PHASE R Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W83627UHG/NCT6627UD HDS DS1 DS0 HDS DS1 DS0 -99- REMARKS Sector ID information after ...
Page 109
... D ------------------------ Execution W ---------------------- C ------------------------ for Each W ---------------------- H ------------------------ Sector: W ---------------------- R ------------------------ (Repeat) W ---------------------- N ------------------------ -------------------- ST0 ----------------------- Result R R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- (10) Recalibrate PHASE R Command W83627UHG/NCT6627UD HDS DS1 DS0 Command codes -100- REMARKS Data transfer between the FDD and system Status information after command execution ...
Page 110
... Seek PHASE R Command -------------------- NCN ----------------------- Execution R (14) Configure PHASE R Command EIS EFIFO POLL | ------ FIFOTHR ----| W | --------------------PRETRK ----------------------- | Execution (15) Relative Seek PHASE R Command W 1 DIR W83627UHG/NCT6627UD DS1 DS0 Head retracted to Track 0 Interrupt Command code Status information at the end of each seek operation Command codes Command codes ...
Page 111
... HUT -------- R ----------- HLT -----------------------------------| ND R ------------------------ SC/EOT ---------------------- R LOCK 0 R 11. EIS EFIFO POLL | ------ FIFOTHR ----- R -----------------------PRETRK ------------------------- (17) Perpendicular Mode PHASE R Command (18) Lock PHASE R Command W LOCK 0 0 Result (19) Sense Drive Status PHASE R Command Result R ---------------- ST3 ------------------------- (20) Invalid PHASE R Command W ------------- Invalid Codes ----------------- W83627UHG/NCT6627UD HDS DS1 DS0 GAP WG --- GAP LOCK ...
Page 112
... INIT PENDING. Indicates the value of the floppy disk interrupt output. 6 DRV2 second drive has been installed second drive is installed. 5 STEP. Indicates the complement of the STEP# output. 4 TRAK0#. Indicates the value of the TRAK# input. W83627UHG/NCT6627UD ST0 = 80H Table 9-2 FDC Registers REGISTER ...
Page 113
... Outward direction. 9.2.2 Status Register B (SB Register) (Read base address + 1) Along with the SA register, the SB register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows BIT W83627UHG/NCT6627UD DESCRIPTION STEP F/F TRAK0 ...
Page 114
... Digital Output Register (DO Register) (Write base address + 2) The Digital Output Register is a write-only register that controls drive motors, drive selection, DRQ/IRQ enable, and FDC reset. All the bits in this register are cleared by the MR pin. The bit definitions are as follows: W83627UHG/NCT6627UD 5 4 ...
Page 115
... NAME NA NA DEFAULT BIT 7-2 RESERVED. 1 Tape sel 1. 0 Tape sel 0. If the three-mode FDD function is enabled (EN3MODE = 1 in LD0 CRF0, Bit 0), the bit definitions are as follows BIT NAME Media ID1 Media ID0 W83627UHG/NCT6627UD MOTOR DMA&INT FDC ENABLE A ENABLE RESET DESCRIPTION 5 4 ...
Page 116
... BIT 7 Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor. 6 DATA INPUT/OUTPUT (DIO). If DIO = HIGH, then the transfer is from Data Register to the processor. If DIO = LOW, the transfer is from processor to Data Register. W83627UHG/NCT6627UD DESCRIPTION Reflect the bit in LD0, CRF2 ...
Page 117
... S/W RESET. The software reset bit. 6 POWER DOWN. 0: FDC in normal mode. 1: FDC in power-down mode PRECOMP 2. 3 PRECOMP 1. 2 PRECOMP 0. 1 DRATE 1. W83627UHG/NCT6627UD DESCRIPTION PRECOMP2 PRECOMP1 PRECOMP0 DESCRIPTION Selects the value of write precompensation. The following precompensation combination of these bits. Please see the tables below ...
Page 118
... W83627UHG, this register is disabled after reset. The FIFO can enable it and change its values through the configure command BIT SE Seek NAME IC Interrupt Code Status Register 0 (ST0) W83627UHG/NCT6627UD DESCRIPTION 0 1: 300 KB/S (MFM), 150 KB/S (FM), RWC 250 KB/S (MFM), 125 KB/S (FM), RWC MB/S (MFM), Illegal (FM), RWC PRECOMPENSATION DELAY 250K – 1 Mbps Default Delays 41 ...
Page 119
... Not Used. This bit is always (Data Error). 1 will be written to this bit if the FDC detects a CRC error in either the ID field or the data field (Over Run). 1 will be written to this bit if the FDC is not served by the host system within a certain time interval during data transfer. W83627UHG/NCT6627UD DESCRIPTION ...
Page 120
... During execution of the Scan command error (Bad Cylinder). 1: Bad Cylinder error (Missing Address Mark in Data Field FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media error. Status Register 3 (ST3 BIT NAME FT WP W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION ...
Page 121
... RESERVED. Reserved for the hard disk controller. During a read of this register, these bits are in tri-state. In PS/2 mode, the bit definitions are as follows BIT NAME DSKCHG 0 1 DEFAULT BIT 7 DSKCHG. Indicates the complement of the DSKCHG# input. 6-3 Always 1 during a read. 2 DRATE 1. W83627UHG/NCT6627UD DESCRIPTION RESERVED DESCRIPTION DRATE1 1 ...
Page 122
... Configuration Control Register (CC Register) (Write base address + 7) This register is used to control the data rate. In PC/AT and PS/2 mode, the bit definitions are as follows BIT NAME NA NA DEFAULT BIT 7-2 RESERVED. Should be set to 0. W83627UHG/NCT6627UD DESCRIPTION how the settings correspond to individual data rates DMAEN NOPREC 0 0 ...
Page 123
... RESERVED. Should be set NOPREC. Disables the precompensation function. This bit can be set by the software. 1 DRATE1. 0 DRATE0. W83627UHG/NCT6627UD DESCRIPTION Select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4) for how the settings correspond to individual data rates. ...
Page 124
... PBE (Parity Bit Enable). When this bit is set to logic 1, the transmitter inserts a stop bit between the last data bit and the stop bit of the SOUT, and the receiver checks the parity bit in the same position. W83627UHG/NCT6627UD ...
Page 125
... DLS0 (Data Length Select Bit 0). Defines the number of data bits that are sent or checked in each serial character. DLS1 The following table identifies the remaining UART registers. Each one is described separately in the following sections. W83627UHG/NCT6627UD DESCRIPTION DLS0 DATA LENGTH Publication Release Date: October 26, 2010 ...
Page 126
... Baudrate BHL Bit 8 Divisor Latch BDLAB = 1 High *: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode. W83627UHG/NCT6627UD Table 10-1 Register Summary for UART Bit Number Data RX Data ...
Page 127
... RDR (RBR Data Ready). This bit is set to logical 1 to indicate that the received data are ready to be read by the CPU in the RBR or FIFO. When no data are left in the RBR or FIFO, the bit is set to logical 0. W83627UHG/NCT6627UD TBRE ...
Page 128
... DTR#. 10.2.4 Handshake Status Register (HSR) (Read/Write) This register reflects the current state of four input pins used with handshake peripherals such as modems and records changes on these pins BIT NAME DCD DEFAULT BIT W83627UHG/NCT6627UD INTERNAL IRQ LOOPBACK LOOPBACK ENABLE RI INPUT ENABLE 0 0 ...
Page 129
... RECEIVER FIFO RESET. Setting this bit to logic 1 resets the RX FIFO counter logic to its initial state. This bit is automatically cleared afterwards. 0 FIFO ENABLE. This bit enables 16550 (FIFO) mode. This bit should be set to logic 1 before other UFR bits are programmed. W83627UHG/NCT6627UD DESCRIPTION ...
Page 130
... Interrupt Type priority First UART Receive Status Second RBR Data Ready W83627UHG/NCT6627UD RX FIFO INTERRUPT ACTIVE LEVEL (BYTES INTERRUPT INTERRUPT STATUS STATUS BIT 2 BIT DESCRIPTION These two bits identify the priority level of the pending interrupt, as shown in the table below. INTERRUPT SET AND FUNCTION ...
Page 131
... ERDRI (RBR Data Ready Interrupt Enable). Set this bit to logical 1 to enable the RBR data ready interrupt. RS485 auto flow control (for rev. E only) 12. W83627UHG/NCT6627UD INTERRUPT SET AND FUNCTION Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. ...
Page 132
... Only one global CR2B register, on page 164, relates to the RS485 auto flow control function for UARTA, UARTC, UARTD and URATE. (See the bellowing table) UARTA CR2B_Bit7 RTS485_enable CR2B_Bit3 RTS485_inv_sel W83627UHG/NCT6627UD UARTC UARTD CR2B_Bit6 CR2B_Bit5 CR2B_Bit2 CR2B_Bit1 Publication Release Date: October 26, 2010 ...
Page 133
... The following table lists the registers used in the EPP mode, and identifies the bit map of the parallel port and EPP registers. Some registers are also used in other modes W83627UHG/NCT6627UD PIN ATTRIBUTE SPP EPP O nSTB nWrite I/O PD<7:0> PD<7:0> I nACK Intr I BUSY nWait SLCT Select O nAFD nDStrb I ...
Page 134
... BUSY# stops. 5 PE. A logical 1 means the printer has detected the end of paper. 4 SLCT. A logical 1 means the printer is selected. 3 ERROR#. A logical 0 means the printer has encountered an error condition. W83627UHG/NCT6627UD REGISTER EPP data port 2 (R/W) EPP data port 2 (R/ ...
Page 135
... EPP write cycle. PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address read cycle to be performed and the data to be output to the host CPU. 11.2.5 EPP Data Port 0-3 W83627UHG/NCT6627UD DESCRIPTION ...
Page 136
... The EPP operates on a two-phase cycle. First, the host selects the register within the device for subsequent operations. Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read, and Data Read. All operations on the EPP device are performed asynchronously.\ W83627UHG/NCT6627UD ...
Page 137
... EPP mode (If this option is enabled in the CRF0h to select ECP/EPP mode) 101 Reserved 110 Test mode 111 Configuration mode The mode selection bits are bits 7-5 of the Extended Control Register. W83627UHG/NCT6627UD Table 11-4 ECP Mode Description DESCRIPTION Publication Release Date: October 26, 2010 -128- Revision 1.7 ...
Page 138
... MODE Ecr Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO. Each register (or pair of registers, in some cases) is discussed below. W83627UHG/NCT6627UD Table 11-5 ECP Register Addresses I/O ECP MODES R/W 000-001 Data Register R/W 011 ...
Page 139
... This bit reflects the nFault input. 2-0 These three bits are not implemented and are always logical 1 during a read. 11.3.4 Device Control Register (DCR) The bit definitions are as follows BIT NAME 1 1 DEFAULT W83627UHG/NCT6627UD PD5 PD4 PD3 PD2 Address or RLE 5 ...
Page 140
... However, data in the tFIFO may be displayed on the parallel port data lines. 11.3.8 CNFGA (Configuration Register A) Mode = 111 This register is a read-only register. When it is read, 10H is returned. This indicates that this is an 8-bit implementation. W83627UHG/NCT6627UD DESCRIPTION Publication Release Date: October 26, 2010 -131- Revision 1.7 ...
Page 141
... ECR (Extended Control Register) Mode = all This register controls the extended ECP parallel port functions. The bit definitions are follows BIT MODE MODE NAME 0 0 DEFAULT BIT W83627UHG/NCT6627UD IRQx2 IRQx1 IRQx0 DESCRIPTION IRQ resource Reflects other IRQ resources selected by PnP ...
Page 142
... Disable DMA and all of the service interrupts. Writing a logical 1 to this bit does not cause an interrupt. 1 Full. Read Only. 0: The FIFO has at least one free byte. 1: The FIFO is completely full; it cannot accept another byte. 0 Empty. Read Only. W83627UHG/NCT6627UD DESCRIPTION Publication Release Date: October 26, 2010 -133- Revision 1.7 ...
Page 143
... This signal sets the transfer direction (asserted = reverse, (nReverseRequest) O deasserted = forward). This pin is driven low to place the channel in the reverse direction. nSelectIn (ECPMode) O This signal is always deasserted in ECP mode. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION acknowledge nReverseRequest. Publication Release Date: October 26, 2010 -134- The ...
Page 144
... The FIFO threshold is set in CR5. All data transferred to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used in Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled. W83627UHG/NCT6627UD Publication Release Date: October 26, 2010 -135- ...
Page 145
... The host must set dmaEn and serviceIntr to 0 and also must set the direction and state accordingly in the programmed I/O transfers. The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O empties or fills the FIFO using the appropriate direction and mode. W83627UHG/NCT6627UD Publication Release Date: October 26, 2010 -136- Revision 1.7 ...
Page 146
... Data written to I/O address 60h is sent to the keyboard (unless the keyboard controller is expecting a data byte) through the controller’s input buffer only if the input buffer full bit (in the status register) is logical 0. W83627UHG/NCT6627UD P24 P25 ...
Page 147
... General Purpose Time-out 7 Parity Error 12.4 Commands COMMAND 20h Read Command Byte of Keyboard Controller W83627UHG/NCT6627UD Table 12-1 Bit Map of Status Register DESCRIPTION 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set writing to the system flag bit in the command byte of the keyboard controller ...
Page 148
... Keyboard "Data" line is stuck low 04 Keyboard "Data" line is stuck high Adh Disable Keyboard Interface Aeh Enable Keyboard Interface C0h Read Input Port (P1) and send data to the system W83627UHG/NCT6627UD FUNCTION BIT DEFINITION BIT DEFINITION Publication Release Date: October 26, 2010 -139- Revision 1.7 ...
Page 149
... KCLKS1 KCLKS0 1 0 DEFAULT BIT 7 KCLKS1. 6 KCLKS0. 5-3 RESERVED. 2 P92EN (Port 92 Enable). 1: Enables Port 92 to control GATEA20 and KBRESET. 0: Disables Port 92 functions. 1 HGA20 (Hardware GATEA 20). W83627UHG/NCT6627UD FUNCTION RESERVED P92EN DESCRIPTION Select the KBC clock rate. Bits Reserved 0 1: Reserved KBC clock input is 12 MHz. ...
Page 150
... When the KBC receives an “FE” command, the KBRESET is pulse low for 6 μs (Min.) with a 14 μs (Min.) delay. GATE A20 and KBRESET are controlled by either software or hardware logic, and they are mutually exclusive. Then, GATE A20 and KBRESET are merged with Port92 when the P92EN bit is set. W83627UHG/NCT6627UD DESCRIPTION Publication Release Date: October 26, 2010 -141- ...
Page 151
... SGA20 (Special GATE A20 Control) 1: Drives GATE A20 signal to high. 0: Drives GATE A20 signal to low. 0 PLKBRST# (Pulled-low KBRESET). A logical 1 on this bit causes KBRESET to drive low for 6 μS(Min.) with a 14 μS(Min.) delay. Before issuing another keyboard-reset command, the bit must be cleared. W83627UHG/NCT6627UD RES. (1) RES. (0) RES ...
Page 152
... Power Control Logic This chapter describes how the W83627UHG implements its ACPI function via these power control pins: PSIN# (Pin 68), PSOUT# (Pin 67), SUSB# (i.e. SLP_S3#; Pin 73) and PSON# (Pin 72). The following figure illustrates the relationships. W83627UHG/NCT6627UD Publication Release Date: October 26, 2010 -143- Note.1 ...
Page 153
... PSIN# is held low. The South Bridge controls the SUSB# signal through the PSOUT# signal. The PSON# is directly connected to the power supply to turn on or off the power. Figure 13-2 shows the power on and off sequences. The ACPI state changes from S5 to S0, then to S5 W83627UHG/NCT6627UD PSOUT# PSOUT# PSOUT# ...
Page 154
... Table 13-1 Bit Map of Logical Device A, CR[E4h], bits [6:5] LOGICAL DEVICE A, CR[E4H], BITS[6: W83627UHG/NCT6627UD S0 State DEFINITION System always turns off when it returns from AC power failure System always turns on when it returns from AC power failure System turns off / on when it returns from power failure depending on the state before the power failure ...
Page 155
... The W83627UHG generates a low pulse through the PSOUT# pin to wake up the system when it detects a key code pressed or mouse button clicked. The following sections describe how the W83627UHG works. 13.2.1 Waken up by Keyboard events W83627UHG/NCT6627UD Definition User defines the state to be “on” User defines the state to be “off” ...
Page 156
... One click of the left button One click of the right button Two clicks of the left button Two clicks of the right button. Three control bits (ENMDAT_UP, MSRKEY, MSXKEY) define the combinations of the mouse wake-up events. Please see the following table for the details. W83627UHG/NCT6627UD ...
Page 157
... Figure 13-3 Mechanism of Resume Reset Logic Table 13-3 Timing and Voltage Parameters of RSMRST# NAME PARAMETER V1 5VSB Valid Voltage 5VSB Ineffective Voltage V2 Valid 5VSB to RSMRST# inactive t1 W83627UHG/NCT6627UD MSXKEY (LOGICAL WAKE-UP EVENT DEVICE A, CR[E0H], BIT 1) Any button clicked or any 1 movement. One click of the left or right 0 button ...
Page 158
... The following table shows the definitions of Logical Device A, CR[E6h] bits 3 ~1. LOGICAL DEVICE A, CR[E6H] BIT PWROK_DEL (first stage) (VSB) Set the delay time when rising from PWROK_LP to PWROK_ST 300 ~ 500 mS. 1: 200 ~ 300 mS. W83627UHG/NCT6627UD V4 V6 MIN. MAX. UNIT - 4 ...
Page 159
... No delay time. 10 For example, if Logical Device A, CR[E6h] bit 2 is set to “0” and bits 2~1 are set to “10”, the range of t2 timing is from 396(300 + 96 596(500 + 96) mS. W83627UHG/NCT6627UD DEFINITION 01: Delay 32 ms 11: Delay 250 ms Publication Release Date: October 26, 2010 -150- ...
Page 160
... Figure 14-1 Start Frame Timing with Source Sampled A Low Pulse on IRQ1 H=Host Control SL=Slave Control Note: 2. The Start Frame pulse can be 4-8 clocks wide. 3. The first clock of Start Frame is driven low by the W83627UHG because IRQ1 of the W83627UHG needs an W83627UHG/NCT6627UD IRQ1 FRAME IRQ0 FRAME ...
Page 161
... The W83627UHG starts to drive the SERIRQ line from the beginning of “IRQ0 FRAME” based on the rising edge of PCICLK. The IRQ/Data Frame has a specific numeral order, as shown in Table 14-1. IRQ/DATA FRAME SIGNAL SAMPLED W83627UHG/NCT6627UD Table 14-1 SERIRQ Sampling Periods SERIRQ SAMPLING PERIODS # OF CLOCKS PAST START IRQ0 2 IRQ1 5 SMI# 8 IRQ3 11 IRQ4 14 IRQ5 17 IRQ6 20 IRQ7 ...
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... H=Host Control R=Recovery Note: 1. There may be none, one or more Idle states during the Stop Frame. 2. The Start Frame pulse of next SERIRQ cycle may or may not start immediately after the turn-around clock of the Stop Frame. W83627UHG/NCT6627UD SERIRQ SAMPLING PERIODS # OF CLOCKS PAST START IRQ15 47 ...
Page 163
... WDTO# pin returns to high. Writing a zero will clear the status bit. This bit will also be cleared if LRESET# or PWROK# signal is asserted. Please note that the output type of WDTO# (pin 77) is open-drain. W83627UHG/NCT6627UD Publication Release Date: October 26, 2010 -154- ...
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... Table 16-1 Relative Control Registers of GPIO 25, 26 and 27 that Support Wake-Up Function EVENTROUTE I (PSOUT#) 0: DISABLE 1: ENABLE LDA, GP25 CR[Feh] bit4 LDA, GP26 CR[Feh] bit5 LDA, GP27 CR[Feh] bit6 16.2 Access Channels W83627UHG/NCT6627UD EVENTROUTE II EVENT POLARITY (PME#) 0: DISABLE 0 : RISING 1: ENABLE 1 : FALLING LDA, LD9, CR[Feh] CR[E6h] bit0 bit5 LD9, LDA, CR[Feh] CR[E6h] ...
Page 165
... ADDRESS ABBR 7 6 GSR Base + 0 Base + 1 IOR DAT Base + 2 INV Base + 3 DST Base + 4 W83627UHG/NCT6627UD Table 16-2 GPIO Register Addresses BIT NUMBER Reserved GPIO I/O Register GPIO Data Register GPIO Inversion Register GPIO Status Register Publication Release Date: October 26, 2010 -156 ...
Page 166
... CR 23h. (IPD&Device Power Down; Default F0h) BIT READ / WRITE UARTF Power Down 0: Powered down 1: Not powered down UARTE Power Down 0: Powered down 1: Not powered down W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 0: Powered down 1: Not powered down 0: Powered down 1: Not powered down 0: Powered down 1: Not powered down ...
Page 167
... Note 1 0 Reserved. Note1: Disable FDC interface Pin 5 CTSF# Pin 6 GP64 Pin 7 DSRF# Pin 8 RTSF# Pin 9 DTRF# Pin 10 SINF W83627UHG/NCT6627UD DESCRIPTION s: value by strapping DESCRIPTION Enable FDC interface Pin 5 DRVDEN0 Pin 6 INDEX# Pin 7 MOA# Pin 8 DSA# Pin 9 DIR# Pin 10 STEP# Publication Release Date: October 26, 2010 -158- Revision 1 ...
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... Write 87h to location 2E twice Write 87h to location 4E twice. The corresponding power-on strapping pin is RTSA# (Pin 51). LOCKREG => Enable R/W configuration registers Disable R/W configuration registers. 4 Reserved. W83627UHG/NCT6627UD Enable FDC interface Pin 11 WD# Pin 13 WE# Pin 14 TRAK0# Pin 15 WP# Pin 16 RDATA# Pin 17 ...
Page 169
... Enable UART D legacy mode for IRQ selection. Then HCR register 5 R/W (base address + 4) bit 3 is effective when selecting IRQ Disable UART D legacy mode for IRQ selection. Then HCR register (base address + 4) bit 3 is not effective when selecting IRQ. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -160- Revision 1.7 ...
Page 170
... Power LED pin outputs 1Hz pulse with 50% duty cycle. 11: Power LED pin outputs 0 Reserved 2Ah Pin Select; Default 00h) BIT READ / WRITE Reserved. 7~4 W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION pulse with 50% duty cycle. 4 (VSB Power) DESCRIPTION Publication Release Date: October 26, 2010 -161- Revision 1.7 ...
Page 171
... Invert the behavior of RTSD# pin for RS485 auto flow control. UARTE_RS485_inv_sel (Available only when CR2B_Bit4= not invert the behavior of RTSE# pin for RS485 auto flow control. 1: Invert the behavior of RTSE# pin for RS485 auto flow control. W83627UHG/NCT6627UD DESCRIPTION 2 C interface) GP25, GP26 (Default) SDA, SCL ...
Page 172
... Disable GP27 input de-bouncer. 0: Enable GP26 input de-bouncer Disable GP26 input de-bouncer. 0: Enable GP25 input de-bouncer Disable GP25 input de-bouncer. 3 Reserved. 0: GP27 trigger type :edge GP27 trigger type :level W83627UHG/NCT6627UD DESCRIPTION Bit-0 Pins function Pin 82 Reserved 0 0 Pin 83 Reserved Others GPIO1 Pin 82 IRRX 0 ...
Page 173
... GP26 trigger type :level 0: GP25 trigger type :edge GP25 trigger type :level CR 2Eh. (Default 00h) BIT READ / WRITE 7 Test Mode Bits: Reserved. CR 2Fh. (Default 00h) BIT READ / WRITE 7 Test Mode Bits: Reserved. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -164- Revision 1.7 ...
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... This bit determines the polarity of all FDD interface signals FDD interface signals are active low. 1: FDD interface signals are active high. When this bit is logic 0, it indicates a second drive is installed and reflected in status register A. (PS2 mode only) W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 001: DMA1. 010: DMA2. 011: DMA3. DESCRIPTION ...
Page 175
... FDD C Drive Type. 3 FDD B Drive Type. 1 FDD A Drive Type. CR F4h. (Default 00h) BIT READ / WRITE 7 Reserved. W83627UHG/NCT6627UD DESCRIPTION 1: Drive and Motor select 0 and 1 are swapped. 00: Model 30. 01: PS/2. 10: Reserved. 11: AT Mode 0: Burst Mode is enabled 1: Non-Burst Mode Normal Floppy Mode. 1: Enhanced 3-mode FDD. DESCRIPTION 00: FDD A ...
Page 176
... Drive Type selection (Refer to TABLE B). CR F5h. (Default 00h) BIT READ / WRITE 7 Same as FDD0 of CR F5h. TABLE A DRIVE RATE TABLE SELECT DRTS1 DRTS0 DRATE1 TABLE B W83627UHG/NCT6627UD DESCRIPTION 10: 2 Meg Tape. 11: Reserved. DESCRIPTION DATA RATE SELECTED DATA RATE DRATE0 MFM 1 1 1Meg 0 0 500K 0 1 300K 1 0 ...
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... DTYPE0 DTYPE1 DRVDEN0 (pin SELDEN 0 1 DRATE1 1 0 SELDEN 1 1 DRATE0 W83627UHG/NCT6627UD DRVDEN1 (pin 3) DRIVE TYPE 4/2/1 MB 3.5”“ DRATE0 2/1 MB 5.25” 2/1.6/1 MB 3.5” (3-MODE) DRATE0 DRATE0 DRATE1 Publication Release Date: October 26, 2010 -168- Revision 1.7 ...
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... ECP mode. 2 011: ECP and EPP – 1.9 mode. 100: Printer Mode. 101: EPP – 1.7 and SPP mode. 110: Reserved. 111: ECP and EPP – 1.7 mode. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 001: DMA1. 010: DMA2. 011: DMA3. DESCRIPTION ...
Page 179
... Reserved. 00: UART A clock source is 1.8462 MHz (24 MHz / 13). 01: UART A clock source is 2 MHz (24 MHz / 12). 1 00: UART A clock source is 24 MHz (24 MHz / 1). 00: UART A clock source is 14.769 MHz (24 MHz / 1.625). W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -170- Revision 1.7 ...
Page 180
... RX mode to TX mode. 00: UART B clock source is 1.8462 MHz (24 MHz / 13). 01: UART B clock source is 2 MHz (24 MHz / 12). 1 00: UART B clock source is 24 MHz (24 MHz / 1). 00: UART B clock source is 14.769 MHz (24 MHz / 1.625). W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -171- ...
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... ASK-IR Note: The notation is normal mode in the IR function. 17.5 Logical Device 5 (Keyboard Controller) CR 30h. (Default 01h) BIT READ / WRITE 7~1 Reserved. W83627UHG/NCT6627UD DESCRIPTION IRTX Tri-state Active pulse 1.6 μS Demodulation into SINB/IRRX Active pulse 3/16 bit time Demodulation into SINB/IRRX KHZ clock ...
Page 182
... BIT READ / WRITE KBC clock rate selection 00: Reserved. 7 01: Reserved. 10: 12MHz 11: Reserved. 5~3 Reserved. 0: Port 92 disabled Port 92 enabled. 0: Gate A20 software control Gate A20 hardware speed up. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -173- Revision 1.7 ...
Page 183
... BIT READ / WRITE 0: KBRST# software control KBRST# hardware speeds up. W83627UHG/NCT6627UD DESCRIPTION Publication Release Date: October 26, 2010 -174- Revision 1.7 ...
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... Reserved. 00: UART C clock source is 1.8462 MHz (24 MHz / 13). 01: UART C clock source is 2 MHz (24 MHz / 12). 1 00: UART C clock source is 24 MHz (24 MHz / 1). 00: UART C clock source is 14.769 MHz (24 MHz / 1.625). W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -175- Revision 1.7 ...
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... Bit 7-0 corresponds to GP37-GP30, respectively. Read Only 7 active edge(rising/falling) has been detected Read-Clear active edge(rising/falling) has been detected Reading the status bit clears E4h. (GPIO4 I/O Register; Default FFh) W83627UHG/NCT6627UD DESCRIPTION 1: GPIO4 is active. 1: GPIO3 is active. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -176- Revision 1 ...
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... READ / WRITE GPIO4 Event Status Bits 7-0 correspond to GP47-GP40, respectively. Read Only 7 active edge(rising/falling) has been detected Read-Clear active edge(rising/falling) has been detected Reading the status bit clears W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -177- Revision 1.7 ...
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... The respective bit and the port value are the same. 7 The respective bit and the port value are inverted. (Both Input & Output ports) CR E3h. (Status Register; Default 00h) BIT READ / WRITE W83627UHG/NCT6627UD DESCRIPTION 1: GPIO6 is active. 1: GPIO5 is active. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION ...
Page 188
... No active edge(rising/falling) has been detected Read-Clear active edge(rising/falling) has been detected Reading the status bit clears F5h. (WDTO# and KBC P20 Control Mode Register; Default 00h) BIT READ / WRITE 7~5 Reserved. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -179- ...
Page 189
... Mouse interrupt reset watch-dog timer enable Watchdog timer is not affected by mouse interrupt. 1: Watchdog timer is reset by mouse interrupt. Keyboard interrupt reset watch-dog timer enable Watchdog timer is not affected by keyboard interrupt. 1: Watchdog timer is reset by keyboard interrupt. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -180- Revision 1.7 ...
Page 190
... Trigger WDTO# event. This bit is self-clearing. WDTO# status bit Watchdog timer is running. Write “0” Clear 1: Watchdog timer issues time-out event. 3 These bits select IRQ resource for WDTO#. (02h for SMI# event.) W83627UHG/NCT6627UD DESCRIPTION Publication Release Date: October 26, 2010 -181- Revision 1.7 ...
Page 191
... Bits 7-0 correspond to GP17-GP10, respectively. Read Only 7 active edge(rising/falling) has been detected Read-Clear active edge(rising/falling) has been detected Reading the status bit clears E4h. (GPIO2 I/O Register; Default FFh) W83627UHG/NCT6627UD DESCRIPTION 1: GPIO2 is active. 1: GPIO1 is active. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -182- Revision 1 ...
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... Select Suspend LED mode. 00: Suspend LED pin is driven low. 7 01: Suspend LED pin is tri-stated. 10: Suspend LED pin outputs 1Hz pulse with 50% duty cycle. 11: Suspend LED pin outputs 5~0 Reserved. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION (VBAT power) DESCRIPTION pulse with 50% duty cycle. ...
Page 193
... CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1]) define the combinations of the mouse wake-up events. Please refer to the following table for the details. ENMDAT_UP MSRKEY W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION MSXKEY Wake-up event x 1 Any button clicked or movement. One click of either left or right button ...
Page 194
... Read Only that the system power is turned on. 4 Read-Clear This bit is 1: When power loss occurs and VSB power is on, it indicates that the system power is turned off. If E4[ => This bit is always 0. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -185- ...
Page 195
... GPIO 6 reset source control bit Enable GPIO 6 reset source by LRESET# =1 Disable GPIO 6 reset source by LRESET# GPIO 5 reset source control bit Enable GPIO 5 reset source by LRESET# =1 Disable GPIO 5 reset source by LRESET# W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -186- Revision 1.7 ...
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... Write 1 to this bit will clear CASEOPEN status. This bit will clear the status itself. The function is the same as Index 46h bit 7 of H/W Monitor part. Power-loss Last State Flag. (VBAT OFF. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -187- Revision 1.7 ...
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... Enable Win98 keyboard wake-up. EN_ONPSOUT (VBAT) Disable/Enable to issue a 0.5s delay PSOUT# level when system returns from power loss state and is supposed described CRE4[6:5], logic device A. (for SiS & VIA chipsets) 0: Disable. 1: Enable. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -188- Revision 1.7 ...
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... R / W-Clear Write 1 to clear this status. PME status of the URB IRQ event W-Clear Write 1 to clear this status. CR F4h. (Default 00h) BIT READ / WRITE W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION 0 : Disable PME Enable PME. DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -189- Revision 1.7 ...
Page 199
... Enable PME interrupt of the URB IRQ event. CR F7h. (Default 00h) (VSB Power) BIT READ / WRITE 7~6 Reserved. 0: Disable PME interrupt of the URF IRQ event Enable PME interrupt of the URF IRQ event. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -190- Revision 1.7 ...
Page 200
... Disable GP27 event route to PME Enable GP27 event route to PME#. 0: Disable GP26 event route to PME Enable GP26 event route to PME#. 0: Disable GP25 event route to PME Enable GP25 event route to PME#. W83627UHG/NCT6627UD DESCRIPTION DESCRIPTION Publication Release Date: October 26, 2010 -191- Revision 1.7 ...