NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 64

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

The SMI#/OVT# pin is a multi-function pin. It can be in SMI# mode or in OVT# mode by setting Configuration
Register CR[29h], bit 6 to one or zero, respectively. In OVT# mode, it can monitor temperatures, and it is enabled
or disabled for SYSTIN and CPUTIN by Bank0 Index 18h, bit 6; and Bank0, Index 4Ch, bit 3.
The OVT# pin has two interrupt modes, comparator and interrupt. The modes are illustrated in this figure.
If Bank0, Index 18h, bit 4, and Bank1 Index 52h, bit1 are set to zero, the OVT# pin is in comparator mode. In
comparator mode, the OVT# pin can create an interrupt once the current temperature exceeds T
to create interrupts until the temperature falls below T
exceeded T
If Bank0, Index 18h, bit 4, and Bank1 Index 52h, bit1 are set to one, the OVT# pin is in interrupt mode. In interrupt
mode, the OVT# pin can create an interrupt once the current temperature rises above T
falls below T
generate additional interrupts, even if the temperature remains above T
This interrupt must be reset by reading all the interrupt status registers. The OVT# pin is asserted when an
interrupt is generated and remains asserted until the interrupt is reset.
The purpose of Caseopen function is used to detect whether the computer case has been opened and possibly
tampered with. This feature must function even when there is no 5VSB power. Consequently, the power source
7.7.2 OVT# Interrupt Mode
7.7.3 Caseopen Detection
In this mode, the SMI# pin can create an interrupt when the current temperature rises above T
current temperature falls below T
interrupt, this mode does not generate additional interrupts, even if the temperature remains above T
the temperature falls below T
subsequent events do not generate interrupts. This is illustrated in the figure above.
O
HYST
and has not yet fallen below T
. Once the temperature rises above T
(Comparator Mode; default)
(Interrupt Mode)
Figure 7-21 OVT# Modes of Temperature Inputs
T
HYST
HYST
OVT#
OVT#
To
. This interrupt must be reset by reading all the interrupt status registers, or
HYST
*Interrupt Reset when Temperature sensor registers are read
. Once the temperature rises above T
HYST
.
*
O
HYST
, however, and generates an interrupt, this mode does not
. The OVT# pin is asserted once the temperature has
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W83627UHG/NCT6627UD
*
O
, until the temperature falls below T
Publication Release Date: October 26, 2010
O
, however, and generates an
*
O
or when the temperature
O
O
and continues
or when the
Revision 1.7
O
, until
HYST
.