NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 8

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

List of Figures
Figure 3-1 W83627UHG Block Diagram ........................................................................................... 6
Figure 4-1 W83627UHG Pin Layout ................................................................................................. 7
Figure 6-1 Structure of the Configuration Register ......................................................................... 22
Figure 6-2 Configuration Register ................................................................................................... 24
Figure 7-1 LPC Bus’ Reads from / Writes to Internal Registers...................................................... 29
Figure 7-2 Serial Bus Write to Internal Address Register Followed by the Data Byte .................... 30
Figure 7-3 Serial Bus Read from Internal Address Register........................................................... 31
Figure 7-4 Analog Inputs and Application Circuit of the W83627UHG ........................................... 32
Figure 7-5 Monitoring Temperature from Thermistor...................................................................... 35
Figure 7-6 Monitoring Temperature from Thermal Diode (Voltage Mode)...................................... 35
Figure 7-7 Monitoring Temperature from Thermal Diode ............................................................... 36
Figure 7-8 PECI Illustration ............................................................................................................. 41
Figure 7-9 FANOUT and Corresponding Temperature Sensors in SMART FAN
Figure 7-10 Mechanism of Thermal Cruise
Figure 7-11 Mechanism of Thermal Cruise
Figure 7-12 Mechanism of Fan Speed Cruise
Figure 7-13 FANOUT and Corresponding Temperature Sensor in SMART FAN
Figure 7-14 Setting of SMART FAN
Figure 7-15 SMART FAN
Figure 7-16 SMART FAN
Figure 7-17 SMI Mode of Voltage and Fan Inputs .......................................................................... 52
Figure 7-18 SMI Mode of SYSTIN I ................................................................................................ 53
Figure 7-19 SMI Mode of SYSTIN II ............................................................................................... 54
Figure 7-20 SMI Mode of CPUTIN .................................................................................................. 54
Figure 7-21 OVT# Modes of Temperature Inputs ........................................................................... 55
Figure 7-22 Caseopen Mechanism ................................................................................................. 56
Figure 12-1 Keyboard and Mouse Interface.................................................................................. 137
Figure 13-1 Power Control Mechanism......................................................................................... 144
Figure 13-2 Power Sequence from S5 to S0, then back to S5. .................................................... 145
Figure 13-3 Mechanism of Resume Reset Logic.......................................................................... 148
Figure 14-1 Start Frame Timing with Source Sampled A Low Pulse on IRQ1 ............................. 151
Figure 14-2 Stop Frame Timing with Host Using 17 SERIRQ Sampling Period........................... 153
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III Mechanism (Current Temp. > Target Temp. + Tol.)....................... 49
III Mechanism (Current Temp. < Target Temp. – Tol.)....................... 50
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III......................................................................................... 48
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Mode (PWM Duty Cycle) ........................................ 45
Mode (DC Output Voltage) ..................................... 45
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-VIII-
Mode................................................................... 46
Publication Release Date: October 26, 2010
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I ...................... 44
III ................... 48
Revision 1.7