NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 124

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

10. UART PORT
10.1 Universal Asynchronous Receiver/Transmitter (UART A, B, C, D, E, F)
The UARTs are used to convert parallel data into serial format for transmission and to convert serial data into
parallel format during reception. The serial data format is a start bit, followed by five to eight data bits, a parity bit
(if programmed) and one, one-and-a-half (five-bit format only) or two stop bits. The UARTs are capable of
handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are
also included to use this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate.
Furthermore, the UARTs also include a complete modem control capability and 16-byte FIFOs for reception and
transmission to reduce the number of interrupts presented to the CPU.
10.2 Register Address
The UART Control Register defines and controls the protocol for asynchronous data communications, including
data length, stop bit, parity, and baud rate selection.
DEFAULT
10.2.1 UART Control Register (UCR) (Read/Write)
BIT
NAME
7
6
5
4
3
BIT
BDLAB (Baud Rate Divisor Latch Access Bit). When this bit is set to logic 1, designers
can access the divisor (in 16-bit binary format) from the divisor latches of the baud-rate
generator during a read or write operation. When this bit is set to logic 0, the Receiver
Buffer Register, the Transmitter Buffer Register, and the Interrupt Control Register can be
accessed.
SSE (Set Silence Enable). A logic 1 forces the Serial Output (SOUT) to a silent state (a
logical 0). Only IRTX is affected by this bit; the transmitter is not affected.
PBFE (Parity Bit Fixed Enable). When PBE and PBFE of UCR are both set to logic 1,
(1) if EPE is logic 1, the parity bit is logical 0 when transmitting and checking;
(2) if EPE is logic 0, the parity bit is logical 1 when transmitting and checking.
EPE (Even Parity Enable). When PBE is set to logic 1, this bit counts the number of logic
1’s in the data word bits and determines the parity bit. When this bit is set to logic 1, the
parity bit is set to logic 1 if an even number of logic 1’s are sent or checked. When the bit
is set to logic 0, the parity bit is logic 1, if an odd number of logic 1’s are sent or checked.
PBE (Parity Bit Enable). When this bit is set to logic 1, the transmitter inserts a stop bit
between the last data bit and the stop bit of the SOUT, and the receiver checks the parity
bit in the same position.
BDLAB
7
0
SSE
6
0
PBFE
5
0
DESCRIPTION
EPE
4
0
-115-
PBE
3
0
W83627UHG/NCT6627UD
MSBE
Publication Release Date: October 26, 2010
2
0
DLS1
1
0
DLS0
0
0
Revision 1.7