NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 103

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

At the start of a command, the FIFO is always disabled, and command parameters must be sent based upon the
RQM and DIO bit settings in the Main Status Register. When the FDC enters the command execution phase, it
clears the FIFO off any data to ensure that invalid data are not transferred.
An overrun or underrun terminates the current command and data transfer. Disk writes complete the current
sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the
result phase may be entered.
DMA transfers are enabled by the specify command and are initiated by the FDC when the LDRQ pin is activated
during a data transfer command.
The function of the data separator is to lock onto incoming serial read data. When a lock is achieved, the serial
front-end logic in the chip is provided with a clock that is synchronized with the read data. The synchronized clock,
called the Data Window, is used to internally sample the serial data portion of the bit cell, and the alternate state
samples the clock portion. Serial-to-parallel conversion logic separates the read data into clock and data bytes.
The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking. The control
logic generates RDD and RWD for every pulse input, and any data pulse input is synchronized and then adjusted
immediately by error adjustment. A digital integrator keeps track of the speed changes in the input data stream.
The write precompensation logic minimizes bit shifts in the RDDATA stream from the disk drive. Shifting of bits is
a known phenomenon in magnetic media and depends on the disk media and the floppy drive.
The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation
are well known, so, depending on the pattern, the bit is shifted either early or late, relative to the surrounding bits.
The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording
differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs
more data bits into the same area.
FDCs with perpendicular recording drives can read standard 3.5” floppy disks and can read and write
perpendicular media. Some manufacturers offer drives that can read and write standard and perpendicular media
in a perpendicular media drive.
A single command puts the FDC into perpendicular mode. All other commands operate as they normally do.
Perpendicular mode requires a 1 Mbps data rate for the FDC, and, at this data rate, the FIFO manages the host
interface bottleneck due to the high speed of data transfer to and from the disk.
9.1.2 Data Separator
9.1.3 Write Precompensation
9.1.4 Perpendicular Recording Mode
9.1.5 FDC Core
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W83627UHG/NCT6627UD
Publication Release Date: October 26, 2010
Revision 1.7