NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 5

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

9.
10.
8.79
8.80
8.81
8.82
8.83
8.84
8.85
8.86
8.87
8.88
8.89
8.90
8.91
8.92
8.93
8.94
8.95
8.96
8.97
9.1
9.2
10.1
10.2
FLOPPY DISK CONTROLLER ................................................................................................. 93
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
UART PORT ........................................................................................................................... 115
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
Reserved Registers – Index 52h (Bank 2).......................................................................... 87
Reserved Registers – Index 53h (Bank 2).......................................................................... 87
Reserved Registers – Index 54h (Bank 2).......................................................................... 87
Reserved Registers – Index 55h (Bank 2).......................................................................... 87
Reserved Registers – Index 56h (Bank 2).......................................................................... 87
Interrupt Status Register 3 – Index 50h (Bank 4) ............................................................... 87
SMI# Mask Register 4 – Index 51h (Bank 4) ...................................................................... 87
Reserved Register – Index 52h (Bank 4)............................................................................ 88
BEEP Control Register 3 – Index 53h (Bank 4).................................................................. 88
SYSTIN Temperature Sensor Offset Register – Index 54h (Bank 4) ................................. 89
CPUTIN Temperature Sensor Offset Register – Index 55h (Bank 4)................................. 89
Reserved Registers – Index 56h (Bank 4).......................................................................... 89
Reserved Register – Index 57h-58h (Bank 4) .................................................................... 89
Real Time Hardware Status Register I – Index 59h (Bank 4)............................................. 89
Real Time Hardware Status Register II – Index 5Ah (Bank 4) ........................................... 90
Real Time Hardware Status Register III – Index 5Bh (Bank 4) .......................................... 91
Reserved Register – Index 5Ch – 5Fh (Bank 4)................................................................. 91
Value RAM 2 ⎯ Index 50h-59h (Bank 5) ........................................................................... 91
Reserved Register – Index 50h – 57h (Bank 6).................................................................. 92
FDC Functional Description ................................................................................................ 93
Register Descriptions........................................................................................................ 103
Universal Asynchronous Receiver/Transmitter (UART A, B, C, D, E, F) ......................... 115
Register Address .............................................................................................................. 115
FIFO (Data) .................................................................................................................................93
Data Separator............................................................................................................................94
Write Precompensation ...............................................................................................................94
Perpendicular Recording Mode...................................................................................................94
FDC Core ....................................................................................................................................94
FDC Commands .........................................................................................................................95
Status Register A (SA Register) (Read base address + 0) .......................................................103
Status Register B (SB Register) (Read base address + 1) .......................................................104
Digital Output Register (DO Register) (Write base address + 2)...............................................105
Tape Drive Register (TD Register) (Read base address + 3) ...................................................106
Main Status Register (MS Register) (Read base address + 4) .................................................107
Data Rate Register (DR Register) (Write base address + 4).....................................................108
FIFO Register (R/W base address + 5).....................................................................................109
Digital Input Register (DI Register) (Read base address + 7) ...................................................112
Configuration Control Register (CC Register) (Write base address + 7) ...................................113
UART Control Register (UCR) (Read/Write)............................................................................115
UART Status Register (USR) (Read/Write) .............................................................................118
Handshake Control Register (HCR) (Read/Write) ...................................................................119
Handshake Status Register (HSR) (Read/Write).....................................................................119
This register is used to control the FIFO functions of the UART..............................................120
-V-
Publication Release Date: October 26, 2010
Revision 1.7