NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 122

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

In PS/2 Model 30 mode, the bit definitions are as follows:
This register is used to control the data rate. In PC/AT and PS/2 mode, the bit definitions are as follows:
DEFAULT
DEFAULT
9.2.9 Configuration Control Register (CC Register) (Write base address + 7)
NAME
BIT
BIT
BIT
NAME
6-4
7-2
1
0
7
3
2
1
0
BIT
BIT
DRATE 0.
HIGHDENS#.
0: 500 KB/S or 1 MB/S data rate (high-density FDD).
1: 250 KB/S or 300 KB/S data rate.
DSKCHG. Indicates the status of the DSKCHG# input.
Always 0 during a read.
DMAEN. Indicates the value of DO register, bit 3.
NOPREC. Indicates the value of the NOPREC bit in the CC REGISTER.
DRATE 1.
DRATE 0.
RESERVED. Should be set to 0.
DSKCHG#
NA
7
7
1
NA
6
6
0
NA
5
5
0
RESERVED
DESCRIPTION
DESCRIPTION
DESCRIPTION
NAN
4
4
0
how the settings correspond to individual
data rates.
Select the data rate of the FDC. See DR
register bits 1 and 0 (Data Rate Register
(DR Register) (Write base address +4)) for
how the settings correspond to individual
data rates.
DMAEN
NA
-113-
3
3
0
W83627UHG/NCT6627UD
NOPREC
NA
2
Publication Release Date: October 26, 2010
2
0
DRATE1
DRATE1
1
1
1
1
DRATE0
DRATE0
0
0
0
0
Revision 1.7