NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 164

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

16. GENERAL PURPOSE I/O
The W83627UHG provides 45 input/output ports that can be individually configured to perform a simple basic I/O
function or an alternative, pre-defined function. GPIO ports 1 ~2 are configured through control registers in Logical
Device 9, GPIO ports 3~4 in Logical Device 7, and GPIO ports 5~6 in Logic Device 8. Users can configure each
individual port to be an input or output port by programming respective bit in the selection register ( 0 = output, 1 =
input). Invert port value by setting inversion register ( 0 = non –inverse, 1 = inverse). The port value is read /
written through data registers.
In addition, only GP25, GP26 and GP27 are designed to be able to assert PSOUT# or PME# signal to wake up
the system if any of them has any transitions. The rising or falling edge can be set to perform the wake-up
function. The following table gives a more detailed register map on GP25, GP26 and GP27.
16.1 GPIO Architecture
16.2 Access Channels
GP25
GP26
GP27
Table 16-1 Relative Control Registers of GPIO 25, 26 and 27 that Support Wake-Up Function
LDA,
CR[Feh]
bit4
LDA,
CR[Feh]
bit5
LDA,
CR[Feh]
bit6
EVENTROUTE I
0: DISABLE
1: ENABLE
(PSOUT#)
LDA,
CR[Feh]
bit0
LDA,
CR[Feh]
bit1
LDA,
CR[Feh]
bit2
EVENTROUTE II
0: DISABLE
1: ENABLE
(PME#)
LD9,
CR[E6h]
bit5
LD9,
CR[E6h]
bit6
LD9,
CR[E6h]
bit7
-155-
EVENT POLARITY
W83627UHG/NCT6627UD
1 : FALLING
0 : RISING
Publication Release Date: October 26, 2010
LD9,
CR[E7h]
bit5
LD9,
CR[E7h]
bit6
LD9,
CR[E7h]
bit7
EVENT STATUS
Revision 1.7