NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 167

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CR 24h. (Global Option; Default 0100_0ss0b)
Note1:
Disable FDC interface
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
3~1
BIT
BIT
5
4
0
7
6
5
4
3
2
1
0
Reserved.
Reserved.
Reserved.
Reserved.
CTSF#
GP64
DSRF#
RTSF#
DTRF#
READ / WRITE
READ / WRITE
SINF
Read Only
R / W
R / W
R / W
R / W
R / W
R / W
R / W
UARTD Power Down. 0: Powered down 1: Not powered down
UARTC Power Down. 0: Powered down 1: Not powered down
IPD (Immediate Power Down). When set to 1, the whole chip is put into
power-down mode immediately.
CLKSEL => Input clock rate selection
= 0 The clock input on pin 18 is 24 MHz.
= 1 The clock input on pin 18 is 48 MHz. (Default)
Select output type of SYSFANOUT
=0 SYSFANOUT is Open-drain. (Default)
=1 SYSFANOUT is Push-pull.
Select output type of CPUFANOUT0
=0 CPUFANOUT is Open-drain. (Default)
=1 CPUFANOUT is Push-pull.
ENKBC => Enable keyboard controller
= 0 KBC is disabled after hardware reset.
= 1 KBC is enabled after hardware reset.
This bit is read-only, and it is set or reset by a power-on strapping pin (Pin
54, SOUTA).
ENFDC => Enable FDC interface
= 0 FDC is enabled after hardware reset.
= 1 FDC is disabled after hardware reset.
This bit is set or reset by a power-on strapping pin (Pin 52, DTRA#).
Note 1
Enable FDC interface
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
s: value by strapping
-158-
DESCRIPTION
DESCRIPTION
W83627UHG/NCT6627UD
DRVDEN0
INDEX#
MOA#
DSA#
DIR#
STEP#
Publication Release Date: October 26, 2010
Revision 1.7