NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 131

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
This 8-bit register enables and disables the five types of controller interrupts separately. A selected interrupt can
be enabled by setting the appropriate bit to logical 1. The interrupt system can be totally disabled by setting bits 0
through 3 to logical 0.
DEFAULT
1
0
0
10.2.7 Interrupt Control Register (ICR) (Read/Write)
BIT
NAME
7
6
5
4
3
2
1
0
BIT
12.
1
0
0
ISR
RS485 auto flow control (for rev. E only)
0
0
0
0
EHSRI (Handshake Status Interrupt Enable). Set this bit to logical 1 to enable the
handshake status register interrupt.
EUSRI (UART Receive Status Interrupt Enable). Set this bit to logical 1 to enable the
UART status register interrupt.
ETBREI (TBR Empty Interrupt Enable). Set this bit to logical 1 to enable the TBR empty
interrupt.
ERDRI (RBR Data Ready Interrupt Enable). Set this bit to logical 1 to enable the RBR
data ready interrupt.
0
1
0
0
0
0
7
0
Second
Third
Fourth
6
0
FIFO Data Timeout
TBR Empty
Handshake status
5
0
INTERRUPT SET AND FUNCTION
DESCRIPTION
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
TBR empty
1. TCTS = 1
3. FERI = 1
4
0
EHSRI
-122-
4. TDCD = 1
2. TDSR = 1
3
0
W83627UHG/NCT6627UD
EUSRI
Publication Release Date: October 26, 2010
2
0
Read RBR
1. Write data into TBR
2. Read ISR (if priority is
Read HSR
ETBREI
third)
1
0
ERDRI
0
0
Revision 1.7