NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 130

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

This register reflects the UART interrupt status.
DEFAULT
Bit
10.2.6 Interrupt Status Register (ISR) (Read only)
3
0
0
0
NAME
BIT
7-6
BIT
5
4
3
2
1
0
BIT 7
Bit
2
0
1
1
ISR
0
0
1
1
FIFOS ENABLED. Set to logical 1 when UFR, bit 0 = 1.
0
0
INTERRUPT STATUS BIT 2. In 16450 mode, this bit is logical 0. In 16550 mode, bits 3
and 2 are set to logical 1 when a time-out interrupt is pending. Please see the table
below.
INTERRUPT STATUS BIT 1.
INTERRUPT STATUS BIT 0.
0 IF INTERRUPT PENDING. This bit is logic 1 if there is no interrupt pending. If one of
the interrupt sources has occurred, this bit is set to logical 0.
Bit
1
0
1
0
FIFOS ENABLED
Bit
0
1
0
0
7
0
Interrupt
priority
First
Second
BIT 6
-
0
1
0
1
6
0
Interrupt Type
UART Receive
Status
RBR Data Ready
5
0
-
INTERRUPT SET AND FUNCTION
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
4
0
DESCRIPTION
Interrupt Source
No Interrupt pending
1. OER = 1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active level
reached
INTERRUPT
STATUS
BIT 2
3
0
These two bits identify the priority level of
the pending interrupt, as shown in the table
below.
-121-
2. PBER =1
W83627UHG/NCT6627UD
INTERRUPT
STATUS
01
04
08
14
BIT 1
2
0
Publication Release Date: October 26, 2010
INTERRUPT
STATUS
Clear Interrupt
Read USR
1. Read RBR
2. Read RBR until FIFO
data under active level
BIT 0
1
0
-
INTERRUPT
PENDING
0 IF
0
1
Revision 1.7