W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 123

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BDLAB = 0
BDLAB = 0
BDLAB = 0
BDLAB = 1
BDLAB = 1
Register Address Base
+ 0
+ 0
+ 1
+ 2
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
+ 0
+ 1
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
Interrupt Control
Interrupt Status
Status Register
Buffer Register
UART Control
UART Status
User Defined
Divisor Latch
Divisor Latch
(Read Only)
(Read Only)
(Write Only)
UART FIFO
(Write Only)
Transmitter
Handshake
Handshake
Receiver
Baudrate
Baudrate
Register
Register
Register
Register
Register
Register
Register
Register
Control
Control
Buffer
High
Low
RBR
UCR
HCR
USR
HSR
UDR
TBR
UFR
BHL
BLL
ICR
ISR
RBR Data
RBR Data
RX Data
TX Data
Terminal
Interrupt
(ERDRI)
Interrupt
Toggling
Pending
(DLS0)
(TCTS)
Enable
Enable
Length
Ready
Ready
Ready
Select
(DTR)
(RDR)
FIFO
Bit 0
Bit 0
"0" if
Data
Bit 0
Data
CTS
Bit 0
Bit 0
Bit 8
0
Table 10-1 Register Summary for UART
(ETBREI)
RX Data
Toggling
Interrupt
Interrupt
Request
TX Data
Overrun
(TDSR)
Enable
(DLS1)
Length
Empty
Status
RCVR
(OER)
Bit (0)
Select
(RTS)
Reset
FIFO
Send
Data
Error
DSR
Bit 1
Bit 1
TBR
Bit 1
Bit 1
Bit 1
Bit 9
to
1
Loopback
RI Falling
Stop Bits
Parity Bit
RX Data
TX Data
(EUSRI)
Interrupt
(MSBE)
Interrupt
Multiple
(PBER)
Enable
Enable
(FERI)
Status
Bit (1)
Reset
-112-
Bit 10
XMIT
Edge
FIFO
Input
Error
Bit 2
Bit 2
Bit 2
Bit 2
USR
RI
2
Bit Number
RX Data
Interrupt
Interrupt
Toggling
TX Data
(EHSRI)
No Stop
Bit (2)**
(NSER)
(TDCD)
Enable
Enable
Enable
Status
Select
Parity
(PBE)
Bit 11
Mode
DMA
Error
DCD
Bit 3
Bit 3
HSR
Bit 3
Bit 3
IRQ
Bit
Bit
3
Reserved
Loopback
Detected
RX Data
TX Data
to Send
Internal
Enable
Enable
(EPE)
(SBD)
(CTS)
Parity
Silent
Bit 12
Clear
Even
Bit 4
Bit 4
Byte
Bit 4
Bit 4
4
0
0
W83627UHG
Reversed
RX Data
TX Data
Bit Fixed
Data Set
(TBRE)
Enable
PBFE)
Ready
Empty
(DSR)
Parity
Bit 13
Bit 5
Bit 5
TBR
Bit 5
Bit 5
5
0
0
0
Active Level
RX Data
Interrupt
Indicator
TX Data
Enabled
Silence
(TSRE)
Enable
Empty
FIFOs
(LSB)
(SSE)
Bit 14
Bit 6
Bit 6
TSR
Ring
Bit 6
Bit 6
(RI)
RX
Set
**
6
0
0
Active Level
Data Carrier
Access Bit
Indication
RX Data
Baudrate
(BDLAB)
RX FIFO
(RFEI) **
TX Data
Enabled
Interrupt
Divisor
FIFOs
(MSB)
Detect
(DCD)
Bit 15
Latch
Error
Bit 7
Bit 7
Bit 7
Bit 7
RX
**
7
0
0