W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 64

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If Bank0, Index 18h, bit 6, and Bank2 Index 52h, bit1 are set to zero, the OVT# pin is in comparator
mode. In comparator mode, the OVT# pin can create an interrupt once the current temperature
exceeds T
asserted once the temperature has exceeded T
If Bank0, Index 18h, bit 6, and Bank2 Index 52h, bit1 are set to one, the OVT# pin is in interrupt mode.
In interrupt mode, the OVT# pin can create an interrupt once the current temperature rises above T
or when the temperature falls below T
generates an interrupt, this mode does not generate additional interrupts, even if the temperature
remains above T
the interrupt status registers. The OVT# pin is asserted when an interrupt is generated and remains
asserted until the interrupt is reset.
7.7.3
The purpose of Caseopen function is used to detect whether the computer case has been opened and
possibly tampered with. This feature must function even when there is no 5VSB power. Consequently,
the power source for the circuit is from either Pin 74 (VBAT) or Pin 61 (5VSB). 5VSB is the default
power source. If there is no 5VSB power, the power source is VBAT. This is designed to save power
consumption of the battery.
When the case is closed, CASEOPEN# (Pin 76) must be pulled high by an external 2MΩ resistor that
is connected to VBAT (Pin 74). When the case is opened, CASEOPEN# will be switched from high to
low. Meanwhile, the detection circuit inside the IC latches the signal. As a result, the interrupt status
and the real-time status can be read at the registers next time when the computer is powered. The
status will not be cleared unless Bank 0, Index 46h, bit 7, or CR[E6h] bit 5 at Logical Device A is set to
“1” first and this bit is self-cleared to “0”.
O
Caseopen Detection
and continues to create interrupts until the temperature falls below T
(Comparator Mode; default)
O
, until the temperature falls below T
(Interrupt Mode)
Figure 7-21 OVT# Modes of Temperature Inputs
T
HYST
OVT#
OVT#
To
*Interrupt Reset when Temperature sensor registers are read
HYST
. Once the temperature rises above T
O
*
and has not yet fallen below T
-53-
HYST
. This interrupt must be reset by reading all
*
Publication Release Date: May 25, 2007
W83627UHG
HYST
*
HYST
.
. The OVT# pin is
O
, however, and
Revision 1.0
O