W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 160

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16. GENERAL PURPOSE I/O
16.1 GPIO Architecture
The W83627UHG provides 45 input/output ports that can be individually configured to perform a
simple basic I/O function or an alternative, pre-defined function. GPIO ports 1 ~2 are configured
through control registers in Logical Device 9, GPIO ports 3~4 in Logical Device 7, and GPIO ports 5~6
in Logic Device 8. Users can configure each individual port to be an input or output port by
programming respective bit in the selection register ( 0 = output, 1 = input). Invert port value by setting
inversion register ( 0 = non -inverse, 1 = inverse). The port value is read / written through data
registers.
In addition, only GP25, GP26 and GP27 are designed to be able to assert PSOUT# or PME# signal to
wake up the system if any of them has any transitions. The rising or falling edge can be set to perform
the wake-up function. The following table gives a more detailed register map on GP25, GP26 and
GP27.
16.2 Access Channels
There are two different channels to set up/access the GPIO ports. The first one is the indirect access
via register 2E/2F (4E/4F, it depends by HEFRAS trapping). The registers can be read / written only
when the respective logical device ID and port number are selected.
The other is the direct access through GPIO register table that can be configured by {CR61, CR60} of
logic device 8. The mapped 5 registers are defined in table 11.2. Since the base address is set, the
GPIO number can be selected by writing the group number to GSR [INDEX] (GPIO Select Register,
#1~#6 for GPIO1 ~ GPIO6 respectively; #0 and #7 is invalid for GSR [INDEX]). Then the I/O register,
the Data register and the Inversion register are mapped to addresses Base+0, Base+1 and Base+2
respectively. Only one GPIO can be accessed at one time. The chip will ignore more than one “1”
written in GSR. The most significant bit (MSB) is with higher priority.
GP25
GP26
GP27
Table 16-1 Relative Control Registers of GPIO 25, 26 and 27 that Support Wake-Up Function
LDA,
CR[FEh]
bit4
LDA,
CR[FEh]
bit5
LDA,
CR[FEh]
bit6
EVENTROUTE I
0: DISABLE
1: ENABLE
(PSOUT#)
LDA,
CR[FEh]
bit0
LDA,
CR[FEh]
bit1
LDA,
CR[FEh]
bit2
EVENTROUTE II
0: DISABLE
1: ENABLE
(PME#)
-149-
LD9,
CR[E6h]
bit5
LD9,
CR[E6h]
bit6
LD9,
CR[E6h]
bit7
EVENT POLARITY
1 : FALLING
0 : RISING
Publication Release Date: May 25, 2007
W83627UHG
LD9,
CR[E7h]
bit5
LD9,
CR[E7h]
bit6
LD9,
CR[E7h]
bit7
EVENT STATUS
Revision 1.0