W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 132

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2.4
The address port is available only in EPP mode. Bit definitions are as follows:
The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
operation. The leading edge of IOW# causes an EPP address write cycle to be performed, and the
trailing edge of IOW# latches the data for the duration of the EPP write cycle.
PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address
read cycle to be performed and the data to be output to the host CPU.
11.2.5
These four registers are available only in EPP mode. The bit definitions for each data port are the
same and as follows:
When any EPP data port is accessed, the contents of DB0-DB7 are buffered (non-inverting) and
output to ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP data
write cycle to be performed and the trailing edge of IOW# latches the data for the duration of the EPP
write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read
cycle to be performed and the data to be output to the host CPU.
NAME
NAME
BIT
BIT
EPP Data Port 0-3
EPP Address Port
PD7
PD7
7
7
PD6
PD6
6
6
PD5
PD5
5
5
-121-
PD4
PD4
4
4
PD3
PD3
3
3
Publication Release Date: May 25, 2007
PD2
PD2
2
2
W83627UHG
PD1
PD1
1
1
Revision 1.0
PD0
PD0
0
0