W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 19

no-image

W83627UHG

Manufacturer Part Number
W83627UHG
Description
IC I/O CONTROLLER 128-QFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheets

Specifications of W83627UHG

Applications
PC's, PDA's
Interface
LPC
Voltage - Supply
3.3V, 5V
Package / Case
128-XFQFN
Mounting Type
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W83627UHG
Manufacturer:
FENGHUA
Quantity:
40 000
Part Number:
W83627UHG
Manufacturer:
Winbond
Quantity:
1 000
Part Number:
W83627UHG
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
W83627UHG
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Company:
Part Number:
W83627UHG
Quantity:
68
5.1
5.2
LFRAME#
DRVDEN0
LRESET#
SYMBOL
SYMBOL
SERIRQ
LAD[3:0]
PCICLK
INDEX#
LDRQ#
DSRF#
CLKIN
CTSF#
RTSF#
PME#
MOA#
GP64
DSA#
LPC Interface
FDC Interface
PIN
PIN
24-
19
86
21
22
23
27
29
30
5
6
7
8
I/OD
OD
OD
OD
I/O
I/O
IN
O
I/O
OD
IN
O
IN
IN
IN
IN
I/O
IN
24
tsu
12p3
12tp3
12tp3
24
t
24
t
24
tsp3
tsp3
tsp3
12ts
12
t
Drive Density Select bit 0.
Clear To Send. It is the modem control input. The function of
these pins can be tested by reading bit 4 of the handshake
status register.
This Schmitt-trigger input from the disk drive is active-low when
the head is positioned over the beginning of a track marked by
an index hole. This input pin needs to connect a pulled-up 1-
KΩ resistor to 5V for Floppy Drive compatibility.
General purpose I/O port 6 bit 4.
Motor A On. When set to 0, this pin enables disk drive A. This is
an open-drain output.
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
Drive Select A. When set to 0, this pin enables disk drive A. This
is an open-drain output.
UART F Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
System clock input, either 24MHz or 48MHz. The actual
frequency must be specified in register. The default value is
48MHz.
Generated PME event.
PCI-clock 33-MHz input.
Encoded DMA Request signal.
Serialized IRQ input / output.
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
Indicates the start of a new cycle or the termination of a broken
cycle.
Reset signal. It can be connected to the PCIRST# signal on the
host.
-8-
DESCRIPTION
DESCRIPTION
W83627UHG

Related parts for W83627UHG