W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 128

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Continued
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
10.2.7
This 8-bit register enables and disables the five types of controller interrupts separately. A selected
interrupt can be enabled by setting the appropriate bit to logical 1. The interrupt system can be totally
disabled by setting bits 0 through 3 to logical 0.
Bit
DEFAULT
3
1
0
0
BIT
NAME
7
6
5
4
3
2
1
0
BIT
Bit
2
1
0
0
ISR
Bit
Interrupt Control Register (ICR) (Read/Write)
0
0
0
0
EHSRI (Handshake Status Interrupt Enable). Set this bit to logical 1 to enable the
handshake status register interrupt.
EUSRI (UART Receive Status Interrupt Enable). Set this bit to logical 1 to enable the
UART status register interrupt.
ETBREI (TBR Empty Interrupt Enable). Set this bit to logical 1 to enable the TBR empty
interrupt.
ERDRI (RBR Data Ready Interrupt Enable). Set this bit to logical 1 to enable the RBR
data ready interrupt.
1
0
1
0
Bit
0
0
0
0
7
0
Interrupt
Second
Third
Fourth
priority
6
0
FIFO Data Timeout
TBR Empty
Handshake status
Interrupt Type
5
0
INTERRUPT SET AND FUNCTION
DESCRIPTION
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
TBR empty
1. TCTS = 1
3. FERI = 1
-117-
4
0
Interrupt Source
EHSRI
2. TDSR = 1
4. TDCD = 1
3
0
Publication Release Date: May 25, 2007
EUSRI
2
0
W83627UHG
Read RBR
2. Read ISR (if priority is
Read HSR
1. Write data into TBR
ETBREI
third)
Clear Interrupt
1
0
Revision 1.0
ERDRI
0
0