W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 136

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3.2
Modes 000 (SPP) and 001 (PS/2) (Data Port)
During a write operation, the Data Register latches the contents of the data bus on the rising edge of
the input, and the contents of this register are output to PD0-PD7. During a read operation, ports PD0-
PD7 are read and output to the host. The bit definitions are as follows:
Mode 011 (ECP FIFO-Address/RLE)
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The
hardware at the ECP port transmits this byte to the peripheral automatically. This operation is defined
only for the forward direction. The bit definitions are as follows:
11.3.3
These bits are logical 0 during a read of the Printer Status Register. The bits of this status register are
defined as follows:
11.3.4
The bit definitions are as follows:
DEFAULT
BIT
2-0
NAME
NAME
NAME
NAME
7
6
5
4
3
BIT
BIT
BIT
BIT
Device Status Register (DSR)
Device Control Register (DCR)
Data and ecpAFifo Port
nBusy. This bit reflects the complement of the Busy input.
nAck. This bit reflects the nAck input.
PError. This bit reflects the PError input.
Select. This bit reflects the Select input.
nFault. This bit reflects the nFault input.
These three bits are not implemented and are always logical 1 during a read.
Address/RLE
nBusy
PD7
7
7
7
1
7
nAck
PD6
6
6
6
1
6
Director
PError
PD5
NA
5
5
5
5
ackInEn
DESCRIPTION
Select
-125-
PD4
NA
4
4
4
4
Address or RLE
SelectIn
nFault
PD3
NA
3
3
3
3
Publication Release Date: May 25, 2007
nInit
PD2
NA
2
2
2
1
2
W83627UHG
Autofd
PD1
NA
1
1
1
1
1
Revision 1.0
Strobe
PD0
NA
0
0
0
1
0