W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 140

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Continued
11.3.11
NStrobe (HostClk)
PD<7:0>
nAck (PeriphClk)
Busy (PeriphAck)
PError (nAckReverse)
Select (Xflag)
NautoFd (HostAck)
nFault
(nPeriphReuqest)
nInit
(nReverseRequest)
nSelectIn (ECPMode)
BIT
1
0
NAME
Full. Read Only.
0: The FIFO has at least one free byte.
1: The FIFO is completely full; it cannot accept another byte.
Empty. Read Only.
0: The FIFO contains at least one byte of data.
1: The FIFO is completely empty.
ECP Pin Descriptions
TYPE
I/O
O
O
O
O
I
I
I
I
I
This pin loads data or address into the slave on its asserting edge
during write operations. This signal handshakes with Busy.
These signals contain address, data or RLE data.
This signal indicates valid data driven by the peripheral when
asserted. This signal handshakes with nAutoFd in reverse.
This signal deasserts to indicate that the peripheral can accept
data. In the reverse direction, it indicates whether the data lines
contain ECP command information or data. Normal data are
transferred when Busy (PeriphAck) is high, and an 8-bit command
is transferred when it is low.
This signal is used to acknowledge a change in the direction of the
transfer (asserted = forward). The peripheral drives this signal low
to
nAckReverse to determine when it is permitted to drive the data
bus.
Indicates printer on-line.
Requests a byte of data from the peripheral when it is asserted. In
the forward direction, this signal indicates whether the data lines
contain ECP address or data. Normal data are transferred when
nAutoFd (HostAck) is high, and an 8-bit command is transferred
when it is low.
Generates an error interrupt when it is asserted. This signal is valid
only in the forward direction. The peripheral is permitted (but not
required) to drive this pin low to request a reverse transfer during
ECP mode.
This signal sets the transfer direction (asserted = reverse,
deasserted = forward). This pin is driven low to place the channel
in the reverse direction.
This signal is always deasserted in ECP mode.
acknowledge
DESCRIPTION
-129-
nReverseRequest.
DESCRIPTION
Publication Release Date: May 25, 2007
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