LFXP6C-4TN144C Lattice, LFXP6C-4TN144C Datasheet - Page 141

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

March 2006

Introduction

The LatticeECP™, LatticeEC™ and LatticeXP™ sysIO™ buffers give the designer the ability to easily interface

with other devices using advanced system I/O standards. This technical note describes the sysIO standards avail-

able and how they can be implemented using Lattice’s design software.

sysIO Buffer Overview

The LatticeECP/EC and LatticeXP sysIO interfaces contain multiple Programmable I/O Cells (PIC) blocks. In the

case of the LatticeEC and LatticeECP devices, each PIC contains two Programmable I/Os (PIO), PIOA and PIOB,

connected to their respective sysIO buffers. In the LatticeXP device, each PIC also contains two PIOs, PIOA and

PIOB, but every fourth PIC will have only PIOA. Two adjacent PIOs can be joined to provide a differential I/O pair

(labeled as “T” and “C”).

Each Programmable I/O (PIO) includes a sysIO Buffer and I/O Logic (IOLOGIC). The LatticeECP/EC and Lattic-

eXP sysIO buffers support a variety of single-ended and differential signaling standards. The sysIO buffer also sup-

ports the DQS strobe signal that is required for interfacing with the DDR memory. One of every 16 PIOs in the

LatticeECP/EC and one of every 14 PIOs in the case of the LatticeXP contains a delay element to facilitate the

generation of DQS signals. The DQS signal from the bus is used to strobe the DDR data from the memory into

input register blocks. For more information on the architecture of the sysIO buffer, please refer to the device data

sheets.

The IOLOGIC includes input, output and tristate registers that implement both single data rate (SDR) and double

data rate (DDR) applications along with the necessary clock and data selection logic. Programmable delay lines

and dedicated logic within the IOLOGIC are used to provide the required shift to incoming clock and data signals

and the delay required by DQS inputs in DDR memory. The DDR implementation in the IOLOGIC and the DDR

memory interface support are discussed in more details in Lattice technical note number TN1050, LatticeECP/EC

DDR Usage Guide.

Supported sysIO Standards

The LatticeECP/EC and LatticeXP sysIO buffer supports both single-ended and differential standards. Single-

ended standards can be further subdivided into LVCMOS, LVTTL, PCI and other standards. The buffers support

the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has indi-

vidually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper

latch). Other single-ended standards supported include SSTL and HSTL. Differential standards supported include

LVDS, RSDS, BLVDS, LVPECL, differential SSTL and differential HSTL. Table 8-1 lists the sysIO standards sup-

ported in the Lattice EC/ECP and LatticeXP devices.

LatticeECP/EC and LatticeXP

8-1

sysIO Usage Guide

Technical Note TN1056

tn1056

_03.3

LFXP6C-4TN144C Lattice, LFXP6C-4TN144C Datasheet - Page 141

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