LFXP6C-4TN144C Lattice, LFXP6C-4TN144C Datasheet - Page 189

• Manufacturer Part Number: LFXP6C-4TN144C
• Description: IC FPGA 5.8KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP6C-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 9-9. Pseudo-Dual Port RAM Attributes for LatticeECP/EC and LatticeXP Devices
Users have the option of enabling the output registers for Pseudo-Dual Port RAM (RAM_DP). Figures 8-23 and 8-
24 show the internal timing waveforms for the Pseudo-Dual Port RAM (RAM_DP) with these options.
Figure 9-25. PSEUDO DUAL PORT RAM Timing Diagram – without Output Registers
DATA_WIDTH_W Write Data Word Width
DATA_WIDTH_R
REGMODE
RESETMODE
CSDECODE_W
CSDECODE_R
GSR
WrClockEn
RdClockEn
WrAddress
RdAddress
Attribute
WrClock
RdClock
Data
Q
t
t
t
SUADDR_EBR
SUADDR_EBR
SUDATA_EBR
Read Data Word Width
Register Mode (Pipelining)
Selects the Reset type
Chip Select Decode for Write 000, 001, 010, 011, 100, 101, 110, 111
Chip Select Decode for Read 000, 001, 010, 011, 100, 101, 110, 111
Global Set Reset
t
SUCE_EBR
Description
Data_0
Add_0
t
t
t
HDATA_EBR
HADDR_EBR
HADDR_EBR
Invalid Data
Data_1
Add_1
1, 2, 4, 9, 18, 36
1, 2, 4, 9, 18, 36
NOREG, OUTREG
ASYNC, SYNC
ENABLED, DISABLED
t
9-24
SUCE_EBR
Values
Add_0
LatticeECP/EC and LatticeXP Devices
t
HCE_EBR
t
CO_EBR
Data_0
Add_1
ENABLED
Default
NOREG
Memory Usage Guide
ASYNC
Value
000
000
1
1
Data_2
Add_2
Data_1
Add_2
User Selectable
IPexpress
Through
YES
YES
YES
YES
YES
NO
NO
t
HCE_EBR
Dat
a_2