LFXP6C-4TN144C Lattice, LFXP6C-4TN144C Datasheet - Page 193

• Manufacturer Part Number: LFXP6C-4TN144C
• Description: IC FPGA 5.8KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP6C-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
First In First Out (FIFO, FIFO_DC) – EBR Based
The EBR blocks in the LatticeECP/EC and LatticeXP devices can be configured as First In First Out Memories –
FIFO and FIFO_DC. FIFO has a common clock for both read and write ports and FIFO_DC (or Dual Clock FIFO)
has separate clocks for these ports. IPexpress allows users to generate the Verilog-HDL or VHDL along with an
EDIF netlist for the memory size as per design requirement.
IPexpress generates the FIFO and FIFO_DC memory module as shown in Figures 9-31 and 9-32.
Figure 9-31. FIFO Module Generated by IPexpress
Figure 9-32. FIFO_DC Module Generated by IPexpress
LatticeECP/EC and LatticeXP devices do not have a built in FIFO. These devices have an emulated FIFO and
FIFO_DC. These are emulated by creating a wrapper around the existing RAMs (like RAM_DP). This wrapper also
includes address pointer generation and FIFO flag generation logic which will be implemented external to the EBR
block. Therefore, in addition to the regular EBR usage, there is extra logic for the address pointer generation and
FIFO flag generation.
A clock is always required as only synchronous write is supported. The various ports and their definitions for the
FIFO and FIFO_DC are included in Table 11.
RdClock
WrClock
Reset
Clock
WrEn
RdEn
Data
Reset
WrEn
RdEn
Data
EBR based First-In First-Out
EBR based First-In First-Out
Memory
Memory
FIFO
FIFO
9-28
LatticeECP/EC and LatticeXP Devices
Q
Full
Almost Full
Empty
Almost Empty
Q
Full
Almost Full
Empty
Almost Empty
Memory Usage Guide