LFXP6C-4TN144C Lattice, LFXP6C-4TN144C Datasheet - Page 220

• Manufacturer Part Number: LFXP6C-4TN144C
• Description: IC FPGA 5.8KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP6C-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
February 2007
Introduction
LatticeECP™, LatticeEC™ and LatticeXP™ devices support various Double Data Rate (DDR) and Single Data
Rate (SDR) interfaces using the logic built into the Programmable I/O (PIO). SDR applications capture data on one
edge of a clock while the DDR interfaces capture data on both the rising and falling edges of the clock, thus dou-
bling the performance. This document will address in detail how to utilize the capabilities of the LatticeECP/EC and
LatticeXP devices to implement both generic DDR and DDR memory interfaces.
DDR SDRAM Interfaces Overview
DDR SDRAM interfaces rely on the use of a data strobe signal, called DQS, for high-speed operation. When read-
ing data from the external memory device, data coming into the device is edge aligned with respect to the DQS sig-
nal. This DQS strobe signal needs to be phase shifted 90 degrees before FPGA logic can sample the read data.
When writing to a DDR SDRAM the memory controller (FPGA) must shift the DQS by 90 degrees to center align
with the data signals (DQ). DQ and DQS are bi-directional ports. The same two signals are used for both write and
read operations. A clock signal is also provided to the memory. This clock is provided as a differential clock (CLKP
and CLKN) to minimize duty cycle variations. The memory also uses these clock signals to generate the DQS sig-
nal during a read via a DLL inside the memory. The skew between CLKP or CLKN and the SDRAM-generated
DQS signal is specified in the DDR SDRAM data sheet. Figures 10-1 and 10-2 show DQ and DQS relationships for
read and write cycles.
During read, the DQS signal is LOW for some duration after it comes out of tristate. This state is called Preamble.
The state when the DQS is LOW before it goes into Tristate is the Postamble state. This is the state after the last
valid data transition.
DDR SDRAM also require a Data Mask (DM) signals to mask data bits during write cycles. SDRAM interfaces typ-
ically are implemented with x8, x16 and x32 bits for each DQS signal. Note that the ratio of DQS to data bits is
independent of the overall width of the memory. An 8-bit interface will have one strobe signal.
Figure 10-1. Typical DDR Interface
www.latticesemi.com
(DDR Memory
Controller)
FPGA
COMMAND
CONTROL
CLK/CLKN
ADDRESS
DQ<7:0>
DQS
DM
LatticeECP/EC and LatticeXP
COMMAND
CONTROL
CLK/CLKN
ADDRESS
DQ<7:0>
DQS
10-1
DM
8
X
Y
Z
DDR Usage Guide
DQ<7:0>
DQS
DM
ADDRESS
COMMAND
CONTROL
CLK/CLKN
DDR Memory
Technical Note TN1050
tn1050_03.2