LFXP6C-4TN144C Lattice, LFXP6C-4TN144C Datasheet - Page 258

• Manufacturer Part Number: LFXP6C-4TN144C
• Description: IC FPGA 5.8KLUTS 100I/O 144-TQFP
• Manufacturer: Lattice

Specifications of LFXP6C-4TN144C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
loop divider can be set to an integer value of 1 to 16. The input and output of the feedback divider must be within
the input and output frequency ranges specified in the device data sheet.
Delay Adjustment
The delay adjust circuit provides programmable clock delay. The programmable clock delay allows for step delays
in increments of 250ps (nominal) for a total of 2.00ns lagging or leading. The time delay setting has a tolerance.
See device data sheet for details. Under this mode, CLKOP, CLKOS and CLKOK are identically affected. The delay
adjustment has two modes of operation:
Output Clock (CLKOP) Divider
The CLKOP divider serves the dual purposes of squaring the duty cycle of the VCO output and scaling up the VCO
frequency into the 420MHz to 840MHz range to minimize jitter. Refer to Table 11-3 for CLKOP Divider value.
CLKOK Divider
The CLKOK divider feeds the global clock net. It divides the CLKOP signal of the PLL by the value of the divider. It
can be set to values of 2, 4, 6,....126,128.
PLL Inputs and Outputs
CLKI Input
The CLKI signal is the reference clock for the PLL. It must conform to the specifications in the data sheet in order
for the PLL to operate correctly. The CLKI can be derived from a dedicated dual-purpose pin or from routing.
RST Input
The PLL reset occurs under two conditions. At power-up an internal power-up reset signal from the configuration
block resets the PLL. The user controlled PLL reset signal RST is provided as part of the PLL module that can be
driven by an internally generated reset function or a pin. This RST signal resets all internal PLL counters. When
RST goes inactive, the PLL will start the lock-in process, and will take the t
Note: For LatticeECP/EC, RST must be asserted to re-start the locking process after losing lock. Refer to the Lat-
ticeECP/EC Family Data Sheet for the RST pulse width requirement. For LatticeXP, RST may be tied to GND.
Figure 11-2 shows the timing diagram of the RST Input.
Figure 11-2. RST Input Timing Diagram
CLKFBK Input
The feedback signal to the PLL, which is fed through the feedback divider can be derived from the global clock net,
a dedicated dual-purpose pin, or directly from the CLKOP divider. Feedback must be supplied in order for the PLL
to synchronize the input and output clocks. External feedback allows the designer to compensate for board-level
clock alignment.
CLKOP Output
The sysCLOCK PLL main clock output, CLKOP, is a signal available for selection as a primary clock.
LOCK
• Static Delay Adjustment – In this mode, the user-selected delay is configured at power-up.
• Dynamic Delay Adjustment (DDA) – In this mode, a simple bus is used to configure the delay. The bus
RST
signals are available to the general purpose FPGA.
t
RST
t
LOCK
11-2
sysCLOCK PLL Design and Usage Guide
LOCK
LatticeECP/EC and LatticeXP
time to complete the PLL lock.